Patents by Inventor Tsuyoshi Midorikawa
Tsuyoshi Midorikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096380Abstract: A semiconductor storage device according to an embodiment comprises: a first memory circuit; a second memory circuit having a storage capacity smaller than that of the first memory circuit; a readout line commonly connected to the first memory circuit and the second memory circuit; a sense amplifier configured to compare a voltage of a first bit signal or a second bit signal with a reference voltage, where the first bit signal being inputted from the first memory circuit through the readout line and the second bit signal being inputted from the second memory circuit through the readout line; and a readout conditioning circuit configured to change at least one of an operation timing of the sense amplifier and the reference voltage corresponding to the first bit signal and the second bit signal.Type: ApplicationFiled: March 15, 2023Publication date: March 21, 2024Inventor: Tsuyoshi MIDORIKAWA
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Patent number: 11289155Abstract: According to one embodiment, there is provided a semiconductor memory device including a bit cell, a pair of bit lines and an assist circuit. The pair of bit lines are electrically connected to the bit cell. The assist circuit is configured to be connected to the bit lines and including one or more capacitive elements. A ratio between a parasitic capacitance value of each of the bit lines and a capacitance value of the assist circuit is adjustable.Type: GrantFiled: August 31, 2020Date of Patent: March 29, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Tsuyoshi Midorikawa, Toshiaki Dozaka
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Publication number: 20210280238Abstract: According to one embodiment, there is provided a semiconductor memory device including a bit cell, a pair of bit lines and an assist circuit. The pair of bit lines are electrically connected to the bit cell. The assist circuit is configured to be connected to the bit lines and including one or more capacitive elements. A ratio between a parasitic capacitance value of each of the bit lines and a capacitance value of the assist circuit is adjustable.Type: ApplicationFiled: August 31, 2020Publication date: September 9, 2021Inventors: Tsuyoshi Midorikawa, Toshiaki Dozaka
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Patent number: 10957385Abstract: According to one embodiment, there is provided a semiconductor storage device including bit cells, a pair of bit lines, a word line, a write amplifier, a word line driver, and an assist timing control circuit. The pair of bit lines are electrically connected to the bit cells. The word line is electrically connected to the bit cells. The write amplifier is electrically connected to the pair of bit lines. The word line driver is electrically connected to the word line. The assist timing control circuit has an output side electrically connected to the write amplifier and the word line driver.Type: GrantFiled: August 29, 2019Date of Patent: March 23, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Tsuyoshi Midorikawa
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Publication number: 20200294579Abstract: According to one embodiment, there is provided a semiconductor storage device including bit cells, a pair of bit lines, a word line, a write amplifier, a word line driver, and an assist timing control circuit. The pair of bit lines are electrically connected to the bit cells. The word line is electrically connected to the bit cells. The write amplifier is electrically connected to the pair of bit lines. The word line driver is electrically connected. to the word line. The assist timing control circuit has an output side electrically connected to the write amplifier and the word line driver.Type: ApplicationFiled: August 29, 2019Publication date: September 17, 2020Inventor: Tsuyoshi Midorikawa
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Publication number: 20200082877Abstract: According to one embodiment, there is provided a semiconductor memory device including a memory cell provided with a pair of storage nodes that complementarily store data, a pair of bit lines that are complementarily driven based on data to be written in the memory cell, a word line that performs row selection of the memory cell, a word line driver that drives the word line, a first switch that is able to control connection and disconnection of power supply of the word line driver, wherein a node that connects the word line driver and the first switch is shared with another word line driver.Type: ApplicationFiled: March 11, 2019Publication date: March 12, 2020Inventor: Tsuyoshi Midorikawa
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Publication number: 20160078923Abstract: In an embodiment, a semiconductor memory device includes a memory cell that includes a first inverter having a first input and a first output, and a second inverter having a second input connected to the first output and a second output connected to first input portion. A first bit line that is connected to the first output of the first inverter via a first transmission transistor. A second bit line is connected to the second output of the second inverter via a second transmission transistor. A first p channel MOS transistor has a drain connected to the first bit line, and a gate connected to the second bit line. A second p channel MOS transistor has a drain connected to the second bit line and a gate connected to the first bit line.Type: ApplicationFiled: February 24, 2015Publication date: March 17, 2016Inventor: Tsuyoshi MIDORIKAWA
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Publication number: 20140050018Abstract: According to one embodiment, a semiconductor memory device includes a memory cell provided with a pair of storage nodes which store data in a complementary manner, a pair of bit lines that are driven in a complementary manner based on data written to the memory cell, a word line that selects a row of the memory cell, and a word line potential fixing circuit that fixes a potential of the word line so that the row of the memory cell is not selected when a power supply of the memory cell rises.Type: ApplicationFiled: March 6, 2013Publication date: February 20, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuyoshi MIDORIKAWA, Nobuaki OTSUKA
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Patent number: 8649231Abstract: A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.Type: GrantFiled: August 10, 2011Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Tsuyoshi Midorikawa
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Publication number: 20120147683Abstract: A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.Type: ApplicationFiled: August 10, 2011Publication date: June 14, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tsuyoshi Midorikawa
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Patent number: 7495310Abstract: A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.Type: GrantFiled: May 25, 2005Date of Patent: February 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Douzaka, Shigeyuki Hayakawa, Yutaka Tanaka, Tsuyoshi Midorikawa
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Publication number: 20050280495Abstract: A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.Type: ApplicationFiled: May 25, 2005Publication date: December 22, 2005Inventors: Toshiaki Douzaka, Shigeyuki Hayakawa, Yutaka Tanaka, Tsuyoshi Midorikawa
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Patent number: 6977834Abstract: A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.Type: GrantFiled: January 29, 2004Date of Patent: December 20, 2005Assignee: Kabush″ei Kaishr ToshibaInventors: Tadashi Onizawa, Tsuyoshi Midorikawa, Shigeyuki Hayakawa, Yutaka Tanaka
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Publication number: 20050111267Abstract: A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.Type: ApplicationFiled: January 29, 2004Publication date: May 26, 2005Inventors: Tadashi Onizawa, Tsuyoshi Midorikawa, Shigeyuki Hayakawa, Yutaka Tanaka
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Patent number: 6418520Abstract: Object of the present invention is to provide an address converting circuit capable of converting a virtual address that access is required into a physical address. The address converting circuit of the present invention has a CLA circuit, an adder, a CAM, a carryout selector, a physical address storing section, and a physical address selector. When adding both of the upper bit strings of the base address and the offset address that access is required, before the carryout signal from the lower bit string is calculated, addition of both of the upper bit strings in case of presuming the carryout signal as “0” and addition of both of the upper bit strings in case of presuming the carryout signal as “1” are performed. Either of the added results is selected by the carryout signal in order to perform the comparing process. Because of this, it is possible to convert into the physical address at high speed.Type: GrantFiled: July 24, 2000Date of Patent: July 9, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Shigeyuki Hayakawa, Tsuyoshi Midorikawa