Patents by Inventor Tsuyoshi Motokurumada
Tsuyoshi Motokurumada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9442836Abstract: An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.Type: GrantFiled: August 21, 2014Date of Patent: September 13, 2016Assignee: FUJITSU LIMITEDInventors: Shuji Yamamura, Masaharu Maruyama, Toshio Yoshida, Ryuji Kan, Naohiro Kiyota, Mikio Hondo, Tsuyoshi Motokurumada
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Patent number: 9063929Abstract: A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.Type: GrantFiled: July 8, 2013Date of Patent: June 23, 2015Assignee: FUJITSU LIMITEDInventors: Kazue Saeki, Masahiro Doteguchi, Tsuyoshi Motokurumada
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Publication number: 20150089180Abstract: An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.Type: ApplicationFiled: August 21, 2014Publication date: March 26, 2015Inventors: Shuji Yamamura, Masaharu Maruyama, Toshio Yoshida, RYUJI KAN, NAOHIRO KIYOTA, Mikio Hondo, TSUYOSHI MOTOKURUMADA
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Patent number: 8700947Abstract: A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.Type: GrantFiled: December 11, 2009Date of Patent: April 15, 2014Assignee: Fujitsu LimitedInventors: Hiroyuki Imai, Naohiro Kiyota, Tsuyoshi Motokurumada
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Publication number: 20140068115Abstract: A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.Type: ApplicationFiled: July 8, 2013Publication date: March 6, 2014Inventors: Kazue SAEKI, Masahiro DOTEGUCHI, Tsuyoshi MOTOKURUMADA
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Patent number: 8464004Abstract: An information processing apparatus, a memory control method, and a memory control device are disclosed, the information processing apparatus including nodes each having a main memory, a processor including a cache memory, and a system controller. The system controller of at least one of the nodes includes a holding unit that holds address information corresponding to primary data stored in the main memory of its local node, and not cached in any of the cache memories of other nodes. The system controller of the at least one node may include local and global snoop control units, as well as a virtual tag expansion (VTAGx) unit, to maintain cache coherency, and under certain conditions, a snoop operation may be skipped or omitted.Type: GrantFiled: December 9, 2008Date of Patent: June 11, 2013Assignee: Fujitsu LimitedInventors: Go Sugizaki, Aiichiro Inoue, Naozumi Aoki, Tsuyoshi Motokurumada
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Publication number: 20100088550Abstract: A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.Type: ApplicationFiled: December 11, 2009Publication date: April 8, 2010Applicant: FUJITSU LIMITEDInventors: Hiroyuki IMAI, Naohiro Kiyota, Tsuyoshi Motokurumada
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Patent number: 7617379Abstract: The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.Type: GrantFiled: November 15, 2004Date of Patent: November 10, 2009Assignee: Fujitsu LimitedInventors: Takahito Hirano, Iwao Yamazaki, Tsuyoshi Motokurumada
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Publication number: 20090240893Abstract: The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes each having a main memory and a processor including a cache memory, the system controller of at least one of the nodes is designed to include a holding unit that holds specific information about primary data present in the main memory of its subject node, with the cache data corresponding to the primary data not present in the cache memory of the nodes other than its subject node. With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved.Type: ApplicationFiled: December 9, 2008Publication date: September 24, 2009Inventors: Go Sugizaki, Aiichiro Inoue, Naozumi Aoki, Tsuyoshi Motokurumada
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Address translation information storing apparatus and address translation information storing method
Patent number: 7587574Abstract: Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.Type: GrantFiled: November 12, 2004Date of Patent: September 8, 2009Assignee: Fujitsu LimitedInventors: Masanori Doi, Iwao Yamazaki, Tsuyoshi Motokurumada, Masahiro Doteguchi -
Publication number: 20080294847Abstract: A cache control device controlling a cache memory having ways based on an access request includes an error number count memory unit that counts the total number of errors occurred in response to the access request regardless of in which way they occur, a degeneration information memory unit that stores cache line degeneration information indicating degeneration of a specific cache line, a degeneration information writing unit that writes, when the counted number of errors reaches a predetermined upper limit number, the cache line degeneration information into the degeneration information memory unit for a cache line, error in which causes the number to reach the predetermined upper limit number, and a replace control unit that performs, in response to a replace request to the cache line corresponding to the cache line degeneration information stored in the degeneration information memory unit, a replace control to exclude the cache line from replace candidates.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Applicant: FUJITSU LIMITEDInventors: Masaharu Maruyama, Tsuyoshi Motokurumada
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Publication number: 20080229011Abstract: A cache memory unit connecting to a main memory system having a cache memory area in which, if memory data that the main memory system has is registered therewith, the registered memory data is accessed by a memory access instruction that accesses the main memory system and a local memory area with which local data to be used by the processing section is registered and in which the registered local data is accessed by a local memory access instruction, which is different from the memory access instruction.Type: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Applicant: FUJITSU LIMITEDInventors: Iwao YAMAZAKI, Tsuyoshi Motokurumada, Hitoshi Sakurai, Hiroyuki Kojima, Tomoyuki Okawa
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Patent number: 7246204Abstract: The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.Type: GrantFiled: February 20, 2003Date of Patent: July 17, 2007Assignee: Fujitsu LimitedInventors: Yuji Shirahige, Tsuyoshi Motokurumada, Masaki Ukai, Aiichiro Inoue
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Publication number: 20060026382Abstract: The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.Type: ApplicationFiled: November 15, 2004Publication date: February 2, 2006Applicant: Fujitsu LimitedInventors: Takahito Hirano, Iwao Yamazaki, Tsuyoshi Motokurumada
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Address translation information storing apparatus and address translation information storing method
Publication number: 20060026381Abstract: Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.Type: ApplicationFiled: November 12, 2004Publication date: February 2, 2006Applicant: Fujitsu LimitedInventors: Masanori Doi, Iwao Yamazaki, Tsuyoshi Motokurumada, Masahiro Doteguchi -
Patent number: 6915406Abstract: A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.Type: GrantFiled: December 30, 2002Date of Patent: July 5, 2005Assignee: Fujitsu LimitedInventors: Takuma Chiba, Tsuyoshi Motokurumada, Iwao Yamazaki
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Publication number: 20040006679Abstract: A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.Type: ApplicationFiled: December 30, 2002Publication date: January 8, 2004Applicant: Fujitsu LimitedInventors: Takuma Chiba, Tsuyoshi Motokurumada, Iwao Yamazaki
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Publication number: 20040003179Abstract: The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.Type: ApplicationFiled: February 20, 2003Publication date: January 1, 2004Applicant: Fujitsu LimitedInventors: Yuji Shirahige, Tsuyoshi Motokurumada, Masaki Ukai, Aiichiro Inoue