Patents by Inventor Tsuyoshi Ujihara

Tsuyoshi Ujihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compound semiconductor multilayer structure, hall device, and hall device manufacturing method
    Patent number: 7388268
    Abstract: Hall device is provided by enabling stable provision of a quantum well compound semiconductor stacked structure. It has first and second compound semiconductor layers composed of Sb and at least two of five elements of Al, Ga, In, As and P, and an active layer composed of InxGa1-xAsySb1-y (0.8?x?1.0, 0.8?y?1.0), which are stacked. Compared with the active layer, the first and second compound semiconductor layers each have a wider band gap, and a resistance value five times or more greater. The lattice constant differences between the active layer and the first and second compound semiconductor layers are each designed in a range of 0.0-1.2%, and the thickness of the active layer is designed in a range of 30-100 nm.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: June 17, 2008
    Assignee: Asahi Kasei Electronics Co., Ltd.
    Inventors: Takayuki Watanabe, Yoshihiko Shibata, Tsuyoshi Ujihara, Takashi Yoshida, Akihiko Oyama
  • Compound semiconductor multilayer structure, hall device, and hall device manufacturing method
    Publication number: 20050042814
    Abstract: Hall device is provided by enabling stable provision of a quantum well compound semiconductor stacked structure. It has first and second compound semiconductor layers composed of Sb and at least two of five elements of Al, Ga, In, As and P, and an active layer composed of InxGa1-x,AsySb1-y (0.8?x?1.0, 0.8 <y?1.0), which are stacked. Compared with the active layer, the first and second compound semiconductor layers each have a wider band gap, and a resistance value five times or more greater. The lattice constant differences between the active layer and the first and second compound semiconductor layers are each designed in a range of 0.0-1.2%, and the thickness of the active layer is designed in a range of 30-100 nm.
    Type: Application
    Filed: January 15, 2003
    Publication date: February 24, 2005
    Inventors: Takayuki Watanabe, Yoshihiko Shibata, Tsuyoshi Ujihara, Takashi Yoshida, Akihiko Oyama