Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.

Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.

Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.

Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.

Abstract: A process for manufacturing a semiconductor device comprising: a substrate having an insulating layer and a semiconductor layer lying on the insulating layer, the semiconductor layer having been divided to form a plurality of isolated semiconductor lands by trenches extending through the semiconductor layer to the insulating layer; integrated circuits formed on the respective lands; and conductors running above and across the trenches to electrically connect the integrated circuits on the isolated semiconductor lands.

Abstract: A method of producing a semiconductor device comprising a bipolar transistor and a MOSFET (e.g., a Bi-MOS device), comprising the steps of: forming an insulating layer on an epitaxial silicon layer on a semiconductor substrate; forming a gate electrode; forming a base region; forming a PSG (an impurity containing glass) layer on the whole surface; carrying out a heat-treatment on the PSG to cause a softening and flow thereof (sloping ends of and flattening the PSG layer); opening collector, emitter, source and drain contact windows in the PSG layer and the insulating layer; forming a doped polysilicon layer over the contact windows with the formation of an emitter region; opening a base contact window; and forming metal (Al) electrodes.

Abstract: A semiconductor device having a submicron miniaturization level structure comprises a first high-current bipolar transistor having a first wide emitter width and a second high-speed bipolar transistor having a narrow emitter width relatively to the first emitter width, which transistors are formed in a second common semiconductor substrate. According to a first embodiment, the base region of the first transistor is thicker than that of the second transistor, and thus a suitable h.sub.Fe balance is maintained; and according to another embodiment, the first, base region of the first transistor has a higher impurity concentration than the second base region of the second transistor and has the same depth as that of the second base region, so that a suitable h.sub.FE balance is maintained.

Abstract: A method for fabricating a BIMOS device includes steps of forming a first insulator layer on the semiconductor layer in correspondence to a first region, providing a gate electrode of a metal-insulator-semiconductor transistor on the first insulator layer, and providing a base electrode of a bipolar transistor on a second region of the semiconductor layer. The method also includes introducing impurities into the semiconductor layer in the first region using the gate electrode as a mask to form self-aligned source and drain regions, introducing impurities into the base electrode and causing a diffusion of the impurities into the semiconductor layer to form a base region in the second region. Also included are steps of providing a second insulator layer so as to cover the first region and the second region, providing an insulator material on the second insulator in the form of liquid and curing subsequently to form a third insulator layer on the second insulator layer with a planarized top surface.

Abstract: With a trend toward higher operation speed and higher gain of a Bi-MIS semiconductor device, wherein a bipolar transistor and a MIS FET are formed on the same silicon substrate, a wide bandgap material such as silicon carbide or micro-crystalline silicon is utilized as an emitter material of the bipolar transistor and further a gate electrode of the MIS FET is simultaneously formed using the same wide bandgap material. By applying the above method in the manufacturing of the Bi-MIS semiconductor device, a high amplification factor of the bipolar transistor and a high cutoff frequency of the MIS FET thereof can be easily obtained without additional processes.

Abstract: A semiconductor device comprising a deep emitter region having a high withstand voltage between the collector and emitter V.sub.CEO and another element comprising a doped region which should be substantially shallower than the deep emitter region, may be fabricated without losing a well controlled current amplification factor h.sub.FE and a desired characteristic of the other element owing to the shallow doped region, by using a first dopant having a large diffusion coefficient for doping the emitter region and a second dopant having a small diffusion coefficient for doping the shallow-doped region and by carrying out a heat treatment necessary for doping the first dopant into the deep emitter region after the second dopant has been introduced into the shallow doped region so that no further heat treatment is needed after the first dopant has been doped into the deep emitter region during the process for fabricating the semiconductor device.