Patents by Inventor Tung-Chieh Chen
Tung-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11010528Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.Type: GrantFiled: January 12, 2016Date of Patent: May 18, 2021Assignee: SYNOPSYS, INC.Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
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Patent number: 10719653Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.Type: GrantFiled: July 19, 2017Date of Patent: July 21, 2020Assignee: SYNOPSYS, INC.Inventors: Chien-Hung Lu, Chun-Chen Chi, Tung-Chieh Chen, Kai-Chih Chi
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Patent number: 10409943Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.Type: GrantFiled: September 2, 2014Date of Patent: September 10, 2019Assignee: SYNOPSYS, INC.Inventors: Tung-Chieh Chen, Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen
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Publication number: 20170316143Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: Chien-Hung Lu, Chun-Chen Chi, Tung-Chieh Chen, Kai-Chih Chi
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Patent number: 9747406Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.Type: GrantFiled: October 7, 2014Date of Patent: August 29, 2017Assignee: Synopsys, Inc.Inventors: Chien-Hung Lu, Chun-Cheng Chi, Tung-Chieh Chen
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Patent number: 9665679Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.Type: GrantFiled: September 15, 2014Date of Patent: May 30, 2017Assignee: Synopsys, Inc.Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
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Publication number: 20170124245Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.Type: ApplicationFiled: January 12, 2016Publication date: May 4, 2017Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
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Patent number: 9311441Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.Type: GrantFiled: November 14, 2014Date of Patent: April 12, 2016Assignee: Synopsys Taiwan Co., Ltd.Inventors: Jui-Hsiang Liu, Hsin-I Lin, Tung-Chieh Chen
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Patent number: 9286433Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.Type: GrantFiled: November 18, 2013Date of Patent: March 15, 2016Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Tung-Chieh Chen, Hung-Ming Chen, Yi-Peng Weng
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Patent number: 9256706Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.Type: GrantFiled: September 3, 2014Date of Patent: February 9, 2016Assignee: Synopsys Taiwan Co., Ltd.Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
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Publication number: 20150143322Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.Type: ApplicationFiled: November 14, 2014Publication date: May 21, 2015Inventors: Jui-Hsiang Liu, Hsin-I Lin, Tung-Chieh Chen
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Publication number: 20150100938Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.Type: ApplicationFiled: October 7, 2014Publication date: April 9, 2015Inventors: Chien-Hung Lu, Chun-Cheng CHI, Tung-Chieh CHEN
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Publication number: 20150067626Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.Type: ApplicationFiled: September 3, 2014Publication date: March 5, 2015Inventors: Tung-Chieh CHEN, Po-Hsun WU, Po-Hung LIN, Tsung-Yi HO
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Publication number: 20150067632Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.Type: ApplicationFiled: September 2, 2014Publication date: March 5, 2015Inventors: Tung-Chieh CHEN, Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen
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Publication number: 20150007123Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ration for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
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Patent number: 8875081Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.Type: GrantFiled: February 26, 2013Date of Patent: October 28, 2014Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
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Publication number: 20140075402Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.Type: ApplicationFiled: November 18, 2013Publication date: March 13, 2014Applicants: Synopsys, Inc., Synopsys Taiwan Co. Ltd.Inventors: Tung-Chieh Chen, Hung-Ming Chen, Yi-Peng Weng
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Publication number: 20140068542Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.Type: ApplicationFiled: February 26, 2013Publication date: March 6, 2014Applicants: SpringSoft USA, Inc, SpringSoft, Inc.Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
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Patent number: 8661388Abstract: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.Type: GrantFiled: October 1, 2009Date of Patent: February 25, 2014Assignee: Mediatek Inc.Inventors: Tung-Chieh Chen, Ping-Hung Yu, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu
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Patent number: 8607182Abstract: A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints.Type: GrantFiled: May 21, 2012Date of Patent: December 10, 2013Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Tung-Chieh Chen, Hung-Ming Chen, Yi-Peng Weng