Abstract: A signal transmitting element is used to solve the problem that an additional surgery is required to remove the conventional vascular monitoring element after completing the detecting task. The signal transmitting element comprises a body made of a specific biodegradable material. The body includes a signal sensing portion including a structure configured to sense a blood flow information of a blood vessel surrounded and contacted by the body, thereby generating a blood vessel signal; and a signal transmitting portion coupled with the signal sensing portion for receiving the blood vessel signal and including a specific structure configured to convert the blood vessel signal into a transmission signal.

Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.

Abstract: A method is provided for securely accessing code in an external memory. In the method, plaintext code may be stored in internal memory as sets of multiple blocks, each of the multiple blocks having N-bits. The code is encrypted and stored in the external memory. A block cipher having an authenticated encryption mode is used to convert the plaintext code to ciphertext code plus an authentication tag corresponding to each set of the multiple blocks. The external memory is formatted to store the ciphertext and the authentication tag. A translated address for the ciphertext is created from a plaintext address. During a read operation, the generated authentication tag is checked with an expected authentication tag. If the check is successful, the ciphertext code is decrypted and provided to a CPU for execution as plaintext code. In one embodiment, the CPU executes the plaintext code “in place” in the external memory.

Abstract: A method is provided for securely accessing code in an external memory. In the method, plaintext code may be stored in internal memory as sets of multiple blocks, each of the multiple blocks having N-bits. The code is encrypted and stored in the external memory. A block cipher having an authenticated encryption mode is used to convert the plaintext code to ciphertext code plus an authentication tag corresponding to each set of the multiple blocks. The external memory is formatted to store the ciphertext and the authentication tag. A translated address for the ciphertext is created from a plaintext address. During a read operation, the generated authentication tag is checked with an expected authentication tag. If the check is successful, the ciphertext code is decrypted and provided to a CPU for execution as plaintext code. In one embodiment, the CPU executes the plaintext code “in place” in the external memory.

Abstract: A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.

Abstract: A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.

Abstract: A personal video recorder (PVR) system includes a processing unit, a system memory coupled to the processing unit by a system memory bus, and an insertion module being coupled to the processing unit for inserting a packet into a PVR bit stream according to packet information. During a packet insertion operation, the processing unit is for reading data from the system memory, processing the data to generate the packet insertion information, and directly transferring the packet insertion information to the insertion module. By directly transferring the packet insertion information generated by the processing unit to the insertion module, memory bandwidth requirements of the system memory are reduced, and data access of the system memory is improved.

Abstract: A Digitally Video Broadcasting—Handheld (DVB-H) system for performing forward error correction includes: a tuner for receiving a data stream; a base-band receiver, coupled to the tuner, for extracting data bytes of a multi-protocol-encapsulation forward-error-correction (MPE-FEC) frame, and performing syndrome calculation on each extracted data byte to determine a corresponding partial syndrome; and an embedded memory, coupled to the base-band receiver, for accumulating each partial syndrome to determine a complete syndrome; wherein once all syndromes of the MPE-FEC frame are received, the base-band receiver determines corresponding error values and utilizes the error values to forward error correct the MPE-FEC frame.

Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.

Abstract: A DVB-H system for performing forward error correction is disclosed, including: a tuner for receiving a data stream; a base-band receiver, coupled to the tuner, for extracting data bytes of an MPE-FEC frame, and performing syndrome calculation on each extracted data byte to determine a corresponding partial syndrome; an embedded memory, coupled to the base-band receiver, for accumulating each partial syndrome to determine a complete syndrome; wherein once all syndromes of the MPE-FEC frame are received, the base-band receiver determines corresponding error values and utilizes the error values to forward error correct the MPE-FEC frame.

Abstract: An inter-network packet modifier coupled between a first network and a second network for generating an outgoing transport packet forwarded to the second network according to an incoming transport packet received from the first network is disclosed. The inter-network packet modifier includes: a storage device for storing an updated identification information; and a pattern detector for detecting a specific pattern of the incoming transport packet and for exchanging an original identification information of the incoming transport packet with the updated identification information according to the specific pattern to generate the outgoing transport packet; wherein the pattern detector is a dedicated hardware for identification information exchanging.

Abstract: A personal video recorder (PVR) system includes a processing unit, a system memory coupled to the processing unit by a system memory bus, and an insertion module being coupled to the processing unit for inserting a packet into a PVR bit stream according to packet information. During a packet insertion operation, the processing unit is for reading data from the system memory, processing the data to generate the packet insertion information, and directly transferring the packet insertion information to the insertion module. By directly transferring the packet insertion information generated by the processing unit to the insertion module, memory bandwidth requirements of the system memory are reduced, and data access of the system memory is improved.

Abstract: A method of processing a transport stream having a plurality of packets to output a protected transport stream includes providing a set of secret keys having a predetermined number of secret keys; generating a key indication value; selecting a secret key from the set of secret keys according to the key indication value to form a selected secret key; generating an encrypted packet based on the selected secret key and a packet in the transport stream by: encrypting the payload of the packet according to the selected secret key, and storing the key indication value in the sync field; and generating the protected transport stream based on the encrypted packet. Where each packet comprising a packet header and a payload, the packet header comprising a sync field, and the sync field carrying a preset sync pattern.

Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.