Patents by Inventor Tung-Hsing Lee
Tung-Hsing Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140127869Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.Type: ApplicationFiled: January 22, 2014Publication date: May 8, 2014Applicant: MEDIATEK INC.Inventors: Ching-Chung Ko, Tung-Hsing Lee
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Patent number: 8674454Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.Type: GrantFiled: February 20, 2009Date of Patent: March 18, 2014Assignee: Mediatek Inc.Inventors: Ching-Chung Ko, Tung-Hsing Lee
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Publication number: 20140070346Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.Type: ApplicationFiled: March 8, 2013Publication date: March 13, 2014Applicant: MEDIATEK INC.Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Tung-Hsing LEE, Wei-Che HUANG, Yu-Hua HUANG
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Publication number: 20130265121Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.Type: ApplicationFiled: March 14, 2013Publication date: October 10, 2013Applicant: MediaTek Inc.Inventors: Ming-Tzong YANG, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang
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Publication number: 20130009741Abstract: The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern.Type: ApplicationFiled: May 17, 2012Publication date: January 10, 2013Applicant: MEDIATEK INC.Inventors: Cheng-Chou HUNG, Cheng-Jyi CHANG, Tung-Hsing LEE, Wei-Che HUANG
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Publication number: 20130009250Abstract: A semiconductor integrated circuit device including: a diffusion area defined by an isolation region in a substrate; a PMOS transistor comprising a metal gate and a high-k dielectric over the diffusion area and source/drain regions sandwiching the metal gate in a first direction; a plurality of dummy diffusion areas surrounding and spaced apart from the diffusion area; and a plurality of first dummy patterns at the two sides of the PMOS transistor in a second direction perpendicular to the first direction and between the dummy diffusion areas and the diffusion area.Type: ApplicationFiled: May 29, 2012Publication date: January 10, 2013Applicant: MEDIATEK INC.Inventors: Tung-Hsing LEE, Tse-Hsiang HSU, Ching-Chung KO
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Publication number: 20130001734Abstract: A Schottky diode structure includes a semiconductor substrate having an anode region and a cathode region. A lightly doped region with a predetermined conductivity type is in the semiconductor substrate. A metal contact overlies the lightly doped region and corresponds to the cathode region to serve as a cathode. A metal silicide layer is beneath and electrically connected to the metal contact, wherein the metal silicide layer, directly under the metal contact, is in direct contact with the lightly doped region. A heavily doped region with the predetermined conductivity type is in the lightly doped region and corresponds to the anode region to serve as an anode.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Applicant: MEDIATEK INC.Inventors: Ming-Tzong Yang, Tung-Hsing Lee
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Publication number: 20130002375Abstract: A transmission line structure is disclosed. The structure includes at least one signal transmission line and a pair of ground transmission lines embedded in a first level of a dielectric layer on a substrate, wherein the pair of ground transmission lines are on both sides of the signal transmission line. A first ground layer is embedded in a second level lower than the first level of the dielectric layer and a second ground layer is embedded in a third level higher than the first level of the dielectric layer. First and second pairs of via connectors are embedded in the dielectric layer, wherein the first pair of via connectors electrically connects the pair of ground transmission lines to the first ground layer and the second pair of via connectors electrically connects the pair of ground transmission lines to the second ground layer.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Applicant: MEDIATEK INC.Inventors: Ming-Tzong Yang, Tung-Hsing Lee, Kuei-Ti Chan
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Publication number: 20120326263Abstract: A semiconductor diode includes a semiconductor substrate having a lightly doped region with a first conductivity type therein. A first heavily doped region with a second conductivity type opposite to the first conductivity type is in the lightly doped region. A second heavily doped region with the first conductivity type is in the lightly doped region and is in direct contact with the first heavily doped region. A first metal silicide layer is on the semiconductor substrate and is in direct contact with the first heavily doped region. A second metal silicide layer is on the semiconductor substrate and is in direct contact with the second heavily doped region. The second metal silicide layer is spaced apart from the first metal silicide layer.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: MEDIATEK INC.Inventors: Ming-Tzong Yang, Tung-Hsing Lee
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Publication number: 20120313217Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate.Type: ApplicationFiled: January 16, 2012Publication date: December 13, 2012Applicant: MEDIATEK INC.Inventors: Cheng-Chou HUNG, Tung-Hsing LEE, Yu-Hua HUANG, Ming-Tzong YANG
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Patent number: 8212323Abstract: A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.Type: GrantFiled: August 5, 2010Date of Patent: July 3, 2012Assignee: Mediatek Inc.Inventors: Tung-Hsing Lee, Tien-Chang Chang, Yuan-Hung Chung
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Patent number: 8188578Abstract: A seal ring structure disposed along a periphery of an integrated circuit. The seal ring is divided into at least a first portion and a second portion. The second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A deep N well is disposed in a P substrate and is positioned under the second portion. The deep N well reduces the substrate noise coupling.Type: GrantFiled: November 19, 2008Date of Patent: May 29, 2012Assignee: Mediatek Inc.Inventors: Tung-Hsing Lee, Tien-Chang Chang, Yuan-Hung Chung
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Patent number: 8084769Abstract: A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.Type: GrantFiled: February 16, 2007Date of Patent: December 27, 2011Assignee: United Microelectronics Corp.Inventors: Shyh-Fann Ting, Sheng-Hao Lin, Chien-Hsing Lee, Da-Ching Chiou, Sun-Chin Wei, Min-Yi Chang, Cheng-Tung Huang, Tung-Hsing Lee, Tzyy-Ming Cheng
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Patent number: 8043919Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.Type: GrantFiled: November 12, 2007Date of Patent: October 25, 2011Assignee: United Microelectronics Corp.Inventors: Tai-Ju Chen, Tung-Hsing Lee, Da-Kung Lo
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Publication number: 20110133308Abstract: A semiconductor device includes a substrate; an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region; a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate.Type: ApplicationFiled: February 16, 2011Publication date: June 9, 2011Inventors: Kuei-Ti Chan, Tung-Hsing Lee, Augusto Marques, Wen-Chang Lee
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Patent number: 7932581Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.Type: GrantFiled: May 12, 2009Date of Patent: April 26, 2011Assignee: Mediatek Inc.Inventors: Ming-Tzong Yang, Ching-Chung Ko, Tung-Hsing Lee, Zheng Zeng
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Patent number: 7897995Abstract: A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.Type: GrantFiled: April 7, 2009Date of Patent: March 1, 2011Assignee: Mediatek Inc.Inventors: Ming-Tzong Yang, Tao Cheng, Ching-Chung Ko, Tung-Hsing Lee
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Publication number: 20110037121Abstract: An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region, wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region.Type: ApplicationFiled: August 16, 2009Publication date: February 17, 2011Inventors: Tung-Hsing Lee, I-Cheng Lin, Wei-Li Tsao
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Publication number: 20100295146Abstract: A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.Type: ApplicationFiled: August 5, 2010Publication date: November 25, 2010Inventors: Tung-Hsing Lee, Tien-Chang Chang, Yuan-Hung Chung
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Publication number: 20100295150Abstract: A semiconductor device includes a substrate, an inductor wiring pattern on the substrate, and at least one oxide define (OD) dummy feature disposed in the substrate under the inductor wiring pattern.Type: ApplicationFiled: February 11, 2010Publication date: November 25, 2010Inventors: Kuei-Ti Chan, Tung-Hsing Lee