Abstract: A method of treating pancreas damage is provided, the method comprises administrating a pharmaceutical composition to a subject in need thereof. The pharmaceutical composition comprises a plurality of pretreated adipose-derived stem cells and an ester type catechin, wherein the plurality of pretreated adipose-derived stem cells are cultured with the ester type catechin.

Abstract: A crimping apparatus comprising a press module connected with a pressing mold, a translation module, and a pressure control module is disclosed. The press module generates an action force on the pressing mold through a fluid. The translation module is coupled to the press module for driving the press module to move toward a flexible printed circuit having two isolated circuit layers such that one circuit layer is pressed to crimp to the other circuit layer, wherein the pressure control module adjusts the pressure within the press module to maintain a constant force on the pressing mold whereby the pressing mold can generate a constant stress acting on the flexible printed circuit during the crimping process. In addition, the crimping apparatus can be adapted in a roll-to-roll process for crimping two isolated circuit layers of each flexible printed circuit unit arranged on the roll.

Abstract: A use of a pharmaceutical composition in preparing a drug for treating pancreas damage. The pharmaceutical composition comprises pretreated adipose-derived stem cells and ester-type catechin, wherein the pretreated adipose-derived stem cells are obtained by co-culturing ester-type catechin with adipose-derived stem cells.

Abstract: A crimping apparatus comprising a press module connected with a pressing mold, a translation module, and a pressure control module is disclosed. The press module generates an action force on the pressing mold through a fluid. The translation module is coupled to the press module for driving the press module to move toward a flexible printed circuit having two isolated circuit layers such that one circuit layer is pressed to crimp to the other circuit layer, wherein the pressure control module adjusts the pressure within the press module to maintain a constant force on the pressing mold whereby the pressing mold can generate a constant stress acting on the flexible printed circuit during the crimping process. In addition, the crimping apparatus can be adapted in a roll-to-roll process for crimping two isolated circuit layers of each flexible printed circuit unit arranged on the roll.

Abstract: A crimping apparatus comprising a press module connected with a pressing mold, a translation module, and a pressure control module is disclosed. The press module generates an action force on the pressing mold through a fluid. The translation module is coupled to the press module for driving the press module to move toward a flexible printed circuit having two isolated circuit layers such that one circuit layer is pressed to crimp to the other circuit layer, wherein the pressure control module adjusts the pressure within the press module to maintain a constant force on the pressing mold whereby the pressing mold can generate a constant stress acting on the flexible printed circuit during the crimping process. In addition, the crimping apparatus can be adapted in a roll-to-roll process for crimping two isolated circuit layers of each flexible printed circuit unit arranged on the roll.

Abstract: A crimping apparatus comprising a press module connected with a pressing mold, a translation module, and a pressure control module is disclosed. The press module generates an action force on the pressing mold through a fluid. The translation module is coupled to the press module for driving the press module to move toward a flexible printed circuit having two isolated circuit layers such that one circuit layer is pressed to crimp to the other circuit layer, wherein the pressure control module adjusts the pressure within the press module to maintain a constant force on the pressing mold whereby the pressing mold can generate a constant stress acting on the flexible printed circuit during the crimping process. In addition, the crimping apparatus can be adapted in a roll-to-roll process for crimping two isolated circuit layers of each flexible printed circuit unit arranged on the roll.

Abstract: The invention is a therapeutic method for repairing damaged pancreas. The method comprises administrating Epigallocatechin gallate (EGCG) of green tea and a plurality of adipose-derived stem cells (ADSC). And Epigallocatechin gallate (EGCG) of green tea enhances the ability of the adipose-derived stem cells to repair damaged tissue.

Abstract: The present invention is related to a therapeutic compound and its application in repairing diabetes-related cardiac injuries, particularly with providing a therapeutic composition containing the epigallocatechin gallate (EGCG) of green tea and the adipose-derived stem cells. The epigallocatechin gallate (EGCG) of green tea can enhance the ability of the adipose-derived stem cells to repaired damaged tissue. And the application is used for repairing the diabetes-related cardiac injuries.

Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

Abstract: A crimping apparatus comprising a press module connected with a pressing mold, a translation module, and a pressure control module is disclosed. The press module generates an action force on the pressing mold through a fluid. The translation module is coupled to the press module for driving the press module to move toward a flexible printed circuit having two isolated circuit layers such that one circuit layer is pressed to crimp to the other circuit layer, wherein the pressure control module adjusts the pressure within the press module to maintain a constant force on the pressing mold whereby the pressing mold can generate a constant stress acting on the flexible printed circuit during the crimping process. In addition, the crimping apparatus can be adapted in a roll-to-roll process for crimping two isolated circuit layers of each flexible printed circuit unit arranged on the roll.

Abstract: Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.

Abstract: A semiconductor processing method to provide a high quality top oxide layer in charged-trapping NAND and NOR flash memory. The top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method described overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

Abstract: A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.

Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

Abstract: The present invention discloses a multi-phase switching regulator and a control method thereof. The multi-phase switching regulator includes plural power stage circuits, wherein at least one power stage circuit is enabled or disabled according to a phase adding/shedding signal; at least one zero current detection circuit, which is coupled to one of the power stage circuit, for generating a trigger signal according to an inductor current in a corresponding one of the power stage circuits, a zero current reference signal, and an average reference signal; and a phase control circuit controlling the phase adding/shedding operation according to the trigger signal.

Abstract: During formation of a charge trap separation in a semiconductor device, an organic material is formed over a plurality of cells. This organic material is selectively removed in order to create a flat upper surface. An etching process is performed to remove the organic material as well as a charge trap layer formed over the plurality of cells, thereby exposing underlying first oxide layers in each of the cells and forming charge trap separation. Further, because of the selective removal step, the etch results in substantially uniform wing heights among the separated cells.

Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

Abstract: A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.