Patents by Inventor Tung-sun Tung

Tung-sun Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8453086
    Abstract: The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: May 28, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tung-Sun Tung, Tsair-Chin Lin, Bing Zhu
  • Patent number: 8296121
    Abstract: Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: October 23, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, William F. Beausoleil, Tung-Sun Tung, James Tomassetti
  • Patent number: 8160862
    Abstract: Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system during an emulation cycle. Power of the unused resources is controlled during emulation of a design under verification corresponding to the logic design by the emulation system. The resources may be identified as being unused during one or more steps of the emulation cycle. The power of the unused resources may be controlled by at least one of: powering down one or more of the unused resources; disabling one or more of the unused resources; freezing inputs to one or more of the unused resources; or setting inputs to one or more of the unused resources to a constant state. In this manner, power consumption of the emulation system is reduced.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: April 17, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell Grant Poplack, William F. Beausoleil, N. James Tomassetti, Tung-sun Tung
  • Patent number: 8108194
    Abstract: A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bing Zhu, Tsair-Chin Lin, Tung-sun Tung, Jingbo Gao
  • Publication number: 20090271167
    Abstract: A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.
    Type: Application
    Filed: December 30, 2008
    Publication date: October 29, 2009
    Applicant: Cadence Design Systems, Inc.
    Inventors: Bing ZHU, Tsair-Chin Lin, Tung-sun Tung, Jingbo Gao
  • Publication number: 20080270105
    Abstract: Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system.
    Type: Application
    Filed: April 25, 2007
    Publication date: October 30, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Mitchell Grant Poplack, William F. Beausoleil, N. James Tomassetti, Tung-sun Tung
  • Publication number: 20060277509
    Abstract: The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 7, 2006
    Inventors: Tung-sun Tung, Tsair-Chin Lin, Bing Zhu