Abstract: A gapless ferrite structure for circulator or isolator includes a first base having a first flange and a first limit slot surrounded by the first flange, a second base having a second flange and a second limit slot surrounded by the second flange, a ferrite with two ends accommodated in the first limit slot and the second limit slot respectively, two limit magnets installed on the first base and the second base respectively and configured to be corresponsive to the ferrite to generate an attraction force on the ferrite, and two sealing units configured between an end of the ferrite and the first limit slot and between the other end of the ferrite and the second limit slot respectively. In this way, a gapless structure can be formed on a signal transmission path in a circulator or isolator.

Abstract: A cross-coupling structure for dielectric cavity filters includes a base and a tuner. The base is communicated with plural resonant cavities, a side through hole and a blind hole, and has a first channel formed between two adjacent resonant cavities which are not used for producing cross-coupling, and a second channel the resonant cavities formed between two adjacent resonant cavities which are used for producing cross-coupling. The side through hole is penetrated through the base and communicated with the second channel. The blind hole is formed on a wall of the second channel and has an opening facing the side through hole. The tuner is entered into the second channel from the side through hole and extended into the blind hole and can be adjustably moved between the opening of the blind hole and the bottom of the blind hole to set a cross-coupling amount target value.

Abstract: An apparatus and a system are provided. The system includes a top plate electrode, a dielectric layer, a plurality of pixel electrode circuits, and a plurality of detection circuits. A droplet is disposed between the top plate electrode and the dielectric layer. The plurality of pixel electrode circuits are arranged in a two-dimensional array. The pixel electrode circuits in each column of the two-dimensional array are electrically connected to a respective detection circuit of the plurality of detection circuits.

Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.

Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.

Abstract: A method for determining a standard depth value of a marker includes obtaining a maximum depth value of the marker. A reference depth value of the marker is obtained based on a depth image of the marker, and a Z-axis coordinate value of the marker is obtained based on a color image of the marker. When the reference depth value and the Z-axis coordinate value are both less than the maximum depth value, and a difference between the reference depth value and the Z-axis coordinate value is not greater than 0, the depth reference value is set as the standard depth value of the marker; and when the difference is greater than 0, the Z-axis coordinate value is set as the standard depth value of the marker.

Abstract: A variable holder module secures a variety of different expansion cards that may be installed within a computer or other information handling system. The holder module has a multi-sided component that is orientable according to which expansion card is to be secured within the computer. Each side of the component may thus correspond to a different one of the expansion cards. Once the expansion card is determined, a human or robotic picker need only orient component to the side that corresponds to the make/model of the expansion card. The holder module is thus adaptable to secure many different expansion cards that may be installed within the computer.

Abstract: The present invention discloses a new dual polarized array waveguide antenna configured above a signal processing substrate and sequentially including an antenna array substrate, a coupling substrate and a waveguide body. The antenna array substrate includes a plurality of patches, each of which having a first coupling portion and a second coupling portion coupled to the signal processing substrate. The top surface of the coupling substrate includes a plurality of coupling pads corresponding to the patches, and each coupling pad is configured above an intersection area of the first coupling portion and the second coupling portion. The waveguide body includes a plurality of waveguide channels passing through the waveguide body and corresponding to the coupling pads. Each waveguide channel has a first ridge pair and a second ridge pair projecting from wall surfaces.

Abstract: The present invention discloses a new single polarized array waveguide antenna adapted to be configured above a signal processing substrate, and including an antenna array substrate and a waveguide body. The antenna array substrate includes a plurality of antenna units, each of which having a coupling portion and an impedance matching portion. The waveguide body is configured above the antenna array substrate, and includes a plurality of waveguide channels passing through the waveguide body. Each waveguide channel has a first ridge and a second ridge projecting from wall surfaces and arranged opposite to each other. The first ridge has a first lower withdrawn edge on a lower section of the waveguide channel, and the second ridge has a second lower withdrawn edge on the lower section of the waveguide channel.

Abstract: The present invention discloses a new single polarized array waveguide antenna adapted to be configured above a signal processing substrate, and including an antenna array substrate and a waveguide body. The antenna array substrate includes a plurality of antenna units, each of which having a coupling portion and an impedance matching portion. The waveguide body is configured above the antenna array substrate, and includes a plurality of waveguide channels passing through the waveguide body. Each waveguide channel has a first ridge and a second ridge projecting from wall surfaces and arranged opposite to each other. The first ridge has a first lower withdrawn edge on a lower section of the waveguide channel, and the second ridge has a second lower withdrawn edge on the lower section of the waveguide channel.

Abstract: The present invention discloses a new dual polarized array waveguide antenna configured above a signal processing substrate and sequentially including an antenna array substrate, a coupling substrate and a waveguide body. The antenna array substrate includes a plurality of patches, each of which having a first coupling portion and a second coupling portion coupled to the signal processing substrate. The top surface of the coupling substrate includes a plurality of coupling pads corresponding to the patches, and each coupling pad is configured above an intersection area of the first coupling portion and the second coupling portion. The waveguide body includes a plurality of waveguide channels passing through the waveguide body and corresponding to the coupling pads. Each waveguide channel has a first ridge pair and a second ridge pair projecting from wall surfaces.

Abstract: A memory heat dissipation unit is disclosed. The memory heat dissipation unit includes a main body having a first portion, a second portion and a connection portion having two lateral edges separately connected to the first and the second portion. The first and the second portion have at least one first heat-receiving section and at least one second heat-receiving section formed thereon, respectively; and the first and the second heat-receiving section are correspondingly in contact with at least one memory chip each to exchange heat with the chips and accordingly cool the same.

Abstract: A method of manufacturing a memory heat dissipation unit is disclosed. The memory heat dissipation unit includes a main body having a first portion, a second portion and a connection portion having two lateral edges separately connected to the first and the second portion. The first and the second portion have at least one first heat-receiving section and at least one second heat-receiving section formed thereon, respectively; and the first and the second heat-receiving section are correspondingly in contact with at least one memory chip each to exchange heat with the chips and accordingly cool the same. The main body can be quickly formed by stamping processes to enable good heat exchange with the memory chips and reduced manufacturing cost.

Abstract: A memory heat dissipation unit is disclosed. The memory heat dissipation unit includes a main body having a first portion, a second portion and a connection portion having two lateral edges separately connected to the first and the second portion. The first and the second portion have at least one first heat-receiving section and at least one second heat-receiving section formed thereon, respectively; and the first and the second heat-receiving section are correspondingly in contact with at least one memory chip each to exchange heat with the chips and accordingly cool the same.