Patents by Inventor Tuo-Hung Hou
Tuo-Hung Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176587Abstract: A multi-bit analog multiplication and accumulation circuit system, which includes: a plurality of analog multiplication circuits, first to fourth accumulation lines, and a binary place value combiner. Each of the analog multiplication circuits performs multiplications on four-bit input data and four-bit weight data, wherein each of the analog multiplication circuits includes four capacitor and switch arrays for performing multiplications on one bit of the four-bit input data and the four-bit weight data. Each of the accumulation lines outputs an accumulation of multiplications performed by each capacitor switch array of each analog multiplication circuit on one bit of the four-bit input data and the four-bit weight data. The binary place value combiner sums up the accumulated result outputted from the accumulation line with corresponding binary place value.Type: ApplicationFiled: June 23, 2023Publication date: May 30, 2024Inventors: Shyh-Jye JOU, Tuo-Hung HOU, Tian-Sheuan CHANG, Kuan-Chih LIN, Hao ZUO
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Publication number: 20240079051Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.Type: ApplicationFiled: November 8, 2022Publication date: March 7, 2024Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Tuo-Hung Hou, Fu-Cheng Tsai, Jian-Wei Su, Kuo-Hua Tseng
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Publication number: 20240038287Abstract: A metallic ferroelectric metal (MFM) field effect transistor (FET) is disclosed. The metallic ferroelectric metal (MFM) field effect transistor (FET) includes an MFM, a first FET and a second FET. The MFM has a first electrode. The first FET is electrically connected to the first electrode, and has a first gate electrode, wherein the first gate electrode has a first area. The second FET is electrically connected to the first electrode, and has a second gate electrode, wherein the second gate electrode has a second area, and the first area and the second area have a ratio therebetween ranging from 1:50 to 1:2.Type: ApplicationFiled: November 7, 2022Publication date: February 1, 2024Applicant: National YANG MING Chiao Tung UniversityInventors: Tuo-Hung HOU, Ming-Hung Wu
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Patent number: 11741189Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.Type: GrantFiled: January 18, 2023Date of Patent: August 29, 2023Assignee: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Publication number: 20230267973Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.Type: ApplicationFiled: December 5, 2022Publication date: August 24, 2023Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
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Publication number: 20230153375Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Patent number: 11625588Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.Type: GrantFiled: March 4, 2020Date of Patent: April 11, 2023Assignee: Industrial Technology Research InstituteInventors: Tuo-Hung Hou, Shyh-Shyuan Sheu, Jeng-Hua Wei, Heng-Yuan Lee, Ming-Hung Wu
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Patent number: 11599600Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.Type: GrantFiled: September 6, 2020Date of Patent: March 7, 2023Assignee: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Publication number: 20230042789Abstract: A method includes: generating a first sum value at least by a first resistor; generating a first shifted sum value based on the first sum value and a nonlinear function; generating a pulse number based on the first shifted sum value; and changing the first resistor based on the pulse number to adjust the first sum value.Type: ApplicationFiled: October 10, 2022Publication date: February 9, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Tuo-Hung HOU, Chih-Cheng CHANG
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Publication number: 20220383079Abstract: A device includes first and second wires, resistors, and a processor. Input signals are transmitted from the first wires through the resistors to the second wires. The processor receives a sum value of the input signals from one of the second wires, and shifts the sum value by a nonlinear activation function to generate a shifted sum value. The processor calculates a backpropagation value based on the shifted sum value and a target value related to a corresponding input signal of the input signals, and generates a pulse number based on the corresponding input signal of the input signal and the backpropagation value. The processor applies a voltage pulse to one of the resistors related to the corresponding input signal based on the pulse number, in order to modify a value of the corresponding input signal in the input signals to be the same as the target value.Type: ApplicationFiled: July 27, 2022Publication date: December 1, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Tuo-Hung HOU, Chih-Cheng CHANG
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Patent number: 11494619Abstract: A device includes first wires, second wires, resistors, and a processor. Input signals are transmitted from the first wires through the resistors to the second wires. The processor receives a sum value of the input signals from one of the second wires, and shifts the sum value by a nonlinear activation function to generate a shifted sum value. The processor calculates a backpropagation value based on the shifted sum value and a target value, and generates a pulse number based on a corresponding input signal of the input signal and the backpropagation value. Each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value. The processor applies a voltage pulse to one of the resistors related to the corresponding input signal based on the pulse number.Type: GrantFiled: October 17, 2018Date of Patent: November 8, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Tuo-Hung Hou, Chih-Cheng Chang
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Publication number: 20210397675Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.Type: ApplicationFiled: September 6, 2020Publication date: December 23, 2021Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Patent number: 11145356Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.Type: GrantFiled: April 16, 2020Date of Patent: October 12, 2021Assignee: Industrial Technology Research InstituteInventors: Fu-Cheng Tsai, Heng-Yuan Lee, Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou
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Publication number: 20210257017Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.Type: ApplicationFiled: April 16, 2020Publication date: August 19, 2021Applicant: Industrial Technology Research InstituteInventors: Fu-Cheng Tsai, Heng-Yuan Lee, Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou
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Patent number: 11031510Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.Type: GrantFiled: December 16, 2019Date of Patent: June 8, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Tuo-Hung Hou, Samuel C. Pan, Pang-Shiuan Liu
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Publication number: 20210150317Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.Type: ApplicationFiled: March 4, 2020Publication date: May 20, 2021Applicant: Industrial Technology Research InstituteInventors: Tuo-Hung Hou, Shyh-Shyuan Sheu, Jeng-Hua Wei, Heng-Yuan Lee, Ming-Hung Wu
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Patent number: 10902317Abstract: A neural network processing system includes at least one synapse and a neuron circuit. The synapse receives an input signal and has an external weighted value and an internal weighted value, and the internal weighted value has a variation caused by an external stimulus. When the variation of the internal weighted value accumulates to a threshold value, the external weighted value varies and the input signal is multiplied by the external weighted value of the synapse to generate a weighted signal. A neuron circuit is connected with the synapse to receive the weighted signal transmitted by the synapse, and calculates and outputs the weighted signal. The present invention can simultaneously accelerate the prediction and learning functions of the deep learning and realize a hardware neural network with high precision and real-time learning.Type: GrantFiled: July 13, 2017Date of Patent: January 26, 2021Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Tuo-Hung Hou, Chih-Cheng Chang, Jen-Chieh Liu
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Patent number: 10868195Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.Type: GrantFiled: November 19, 2019Date of Patent: December 15, 2020Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Tuo-Hung Hou, Samuel C. Pan, Pang-Shiuan Liu
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Publication number: 20200119204Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Tuo-Hung Hou, Samuel C. Pan, Pang-Shiuan Liu
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Publication number: 20200105943Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.Type: ApplicationFiled: November 19, 2019Publication date: April 2, 2020Inventors: Tuo-Hung HOU, Samuel C. PAN, Pang-Shiuan LIU