Abstract: A CMOS cell architecture and routing method optimized for three or more interconnect layer cell based integrated circuits such as gate arrays is disclosed. Improved provisioning of routing resources and cell layout optimize routability and significantly reduce cell size. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend orthogonally to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire impedances, and reduced noise.