Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Abstract: An integrated circuit for offloading a page migration operation from a host processor is provided. The integrated circuit is configured to: receive, from the host processor, a request to perform the page migration operation from a first physical address to a second physical address; and based on the request, perform the page migration operation. The page migration operation comprises: performing a copy operation of data from the first physical address to the second physical address, and updating a page table entry based on the second physical address, to enable the host processor to access the data from the second physical address based on the updated page table entry.

Abstract: Techniques for obtaining the performance of an integrated circuit design are disclosed. One such technique may retrieve, from a data store, a set of snapshots of a virtual machine of a host system taken during execution of a performance test. For each snapshot in the set of snapshots, the snapshot can be loaded onto a virtual machine running on an emulator that is emulating the integrated circuit design. The virtual machine can be executed for a reduced runtime, and the performances measured during execution of the snapshots can be used to derive the performance of the integrated circuit design.

Abstract: Techniques for reducing the probability of spinlock and/or reducing the time that a virtual central processing unit (CPU) may hold a lock are provided. In one embodiment, a computer-implemented method includes determining that an executing virtual CPU is holding a lock for exclusive use of a resource, and scheduling the executing virtual CPU to run for up to a specified time period before de-scheduling the executing virtual CPU. In one embodiment, the executing virtual CPU holding the lock writes a value to a register to indicate that the executing virtual CPU is holding the lock.

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Abstract: Disclosed is a network device, comprising a first network interface port, a second network interface port, and a processor coupled to the first network interface port and the second network interface port. The processor can be configured to operate in a first switching mode to receive network control packets via the first network interface port and transmit the received network control packets via the second network interface port. The processor can also be configured operate in a second communications mode to receive and transmit network communication packets using the first network interface independently of the operation in the first switching mode.

Abstract: Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.

Abstract: Disclosed is a network device, comprising a first network interface port, a second network interface port, and a processor coupled to the first network interface port and the second network interface port. The processor can be configured to operate in a first switching mode to receive network control packets via the first network interface port and transmit the received network control packets via the second network interface port. The processor can also be configured operate in a second communications mode to receive and transmit network communication packets using the first network interface independently of the operation in the first switching mode.