Abstract: An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are doped with an LDD configuration of phosphorus ions and then a further implantation of arsenic ions is performed. This can conveniently be accomplished by providing an opening in the mask used to implant impurities into the source/drain regions of the ESD protection circuit.

Abstract: The process of the present invention has numerous advantages over the prior art. The silicon nitride side-wall spacers permit a small contact hole thus miniaturizing the cell beyond lithographic limits. The side-wall spacers composed of silicon nitride and silicon dioxide avoid to expose the polysilicon when the contact window is formed by etching step. Moreover, the highly selective etching process improve the accuracy of the contact window.

Abstract: A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.

Abstract: A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.

Abstract: A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over the P-well and N-well regions is provided. The P-well region is implanted, in a substantially vertical direction, with a first conductivity-imparting dopant. Gate structures are formed over the P-well and N-well regions. A second conductivity-imparting dopant is implanted, at a large angle to the plane of the silicon substrate, that is of opposite conductivity to the first conductivity-imparting dopant, into the P-well and N-well regions, masked by the gate structures. The N-well region is implanted, in a substantially vertical direction, with a third conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. Sidewall spacers are formed on the gate structures.