Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first active region extending along a first direction. The semiconductor device also includes a second active region extending along the first direction. The semiconductor device further includes a first gate extending along a second direction perpendicular to the first direction. The first gate has a first segment disposed between the first active region and the second active region. In addition, the semiconductor device includes a first electrical conductor extending along the second direction and across the first active region and the second active region, wherein the first segment of the first gate and the first electrical conductor are partially overlapped to form a first capacitor.

Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.

Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

Abstract: A semiconductor device includes a substrate, a channel layer, a gate structure, source/drain regions, and an insulating layer. The channel layer is disposed over the substrate. The gate structure is disposed over the channel layer. The source/drain regions are disposed over the substrate and disposed at two opposite sides of the channel layer. The insulating layer is disposed between the channel layer and the source/drain regions.

Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: A slide rail assembly includes a first rail, a second rail, a slide assisting device, an elastic member and a working member. The second rail and the first rail are movable relative to each other. The elastic member is arranged on the second rail. During a process of the second rail being moved relative to the first rail along an opening direction, the working member is configured to contact the elastic member in an initial state in order to drive the slide assisting device to move along the opening direction to a predetermined position. When the slide assisting device is located at the predetermined position, the elastic member releases an elastic force through a predetermined space of the first rail, such that the elastic member is no longer in the initial state with the working member no longer contacting the elastic member.

Abstract: A slide rail assembly is provided and includes a first rail, a second rail movable with respect to the first rail, a working member, an operating member and a blocking member. When the second rail is located at an extended position with respect to the first rail and the working member is in a first state, the working member and a blocking feature of the first rail block each other for restraining the second rail from moving toward a first predetermined direction from the extended position. The blocking member is switchable between a blocking state and a non-blocking state for restraining the operating member from driving the working member to disengage from the first state or for allowing the operating member to drive the working member from the first state to a second state. Besides, a related slide rail kit is also provided.

Abstract: An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is measured, so as to provide an alignment offset between the first material layer and the second material layer in addition, a distance between the second alignment mark in the second material layer and a third alignment mark in a third material layer underlying the second material layer is measured, so as to provide an alignment offset between the second material layer and the third material layer. The second alignment marks can be repeatedly used when measuring the alignment accuracy between the first and the second material layers measuring the alignment accuracy between the second and the third material layers.

Abstract: An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is measured, so as to provide an alignment offset between the first material layer and the second material layer. In addition, a distance between the second alignment mark in the second material layer and a third alignment mark in a third material layer underlying the second material layer is measured, so as to provide an alignment offset between the second material layer and the third material layer. Because the second alignment marks can be repeatedly used, scribe line areas for forming these alignment marks and measuring time are saved to increase the production throughput.

Abstract: An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is measured, so as to provide an alignment offset between the first material layer and the second material layer. In addition, a distance between the second alignment mark in the second material layer and a third alignment mark in a third material layer underlying the second material layer is measured, so as to provide an alignment offset between the second material layer and the third material layer. The second alignment marks can be repeatedly used when measuring the alignment accuracy between the first and the second material layers measuring the alignment accuracy between the second and the third material layers, scribe line areas for forming these alignment marks.

Abstract: An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is measured, so as to provide an alignment offset between the first material layer and the second material layer. In addition, a distance between the second alignment mark in the second material layer and a third alignment mark in a third material layer underlying the second material layer is measured, so as to provide an alignment offset between the second material layer and the third material layer. As the second alignment marks can be repeatedly used when measuring the alignment accuracy between the first and the second material layers, and measuring the alignment accuracy between the second and the third material layers, scribe line areas for forming these alignment marks and measuring time are saved to increase the production throughput.