Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.

Abstract: An image sensor device and methods of forming an image sensor device are provided. The image sensor device includes a plurality of image-sensing elements arranged within the device substrate. The image sensor device further includes an isolation grid structure extending into the device substrate and made up of a plurality of isolation grid segments that surround the outer perimeters of the plurality of image-sensing elements. The isolation grid structure includes a passivation liner and a conductive material in contact with the passivation liner. The conductive material may be an indium-tin-oxide film.

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

Abstract: Some implementations described herein provide for techniques to form a biased backside deep trench isolation and grid structure for a backside illumination image sensor. The techniques include forming an array of backside deep trench isolation structures and a biasing-pad that electrically connects to the array of metal-filled backside deep trench isolation structures through the grid structure. The array of backside deep trench isolation structures, the grid structure, and the biasing-pad structure may reduce a likelihood of electrical cross-talk and/or oblique light cross-talk between the photodiodes of the backside illumination image sensor. In this way, a performance of the backside illumination image sensor may be improved. Such improvements may include a suppression of a dark current within the backside illumination image sensor, a reduction in a number of white pixels, and a reduction in cross-talk within the backside illumination image sensor.

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

Abstract: An optical structure and methods of forming an optical structure are provided. In some embodiments, the optical structure includes a substrate having a frontside and a backside opposite the frontside, a plurality of image-sensing elements arranged within the substrate, and a deep trench isolation (DTI) structure disposed between adjacent image-sensing elements. The DTI structure extends from the backside of the substrate to a first depth within the substrate and laterally surrounds the plurality of image-sensing elements. The optical structure further includes a light transmission layer formed over the backside of the substrate. The light transmission layer includes a first side and a second side adjacent to the backside of the substrate. The optical structure further includes a buried grid structure in the light transmission layer, the buried grid structure extending from the first side of the light transmission layer to a second depth within the light transmission layer.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.

Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor with a high full well capacity (FWC). A first integrated circuit (IC) chip and a second IC chip are stacked with each other. The first IC chip comprises a first semiconductor substrate, and the second IC chip comprises a second semiconductor substrate. A pixel sensor is in and spans the first and second IC chips. The pixel sensor comprises a transfer transistor and a pinned photodiode adjoining the transfer transistor at the first semiconductor substrate, and further comprises a plurality of additional transistors (e.g., a reset transistor, a source-follower transistor, etc.) at the second semiconductor substrate. A bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other and are configured to be biased with different voltages (e.g., a negative voltage and ground).

Abstract: The present disclosure describes a three-chip complementary metal-oxide-semiconductor (CMOS) image sensor and a method for forming the image sensor. The image sensor a first chip including a plurality of image sensing elements, transfer transistors and diffusion wells corresponding to the plurality of image sensing elements, a ground node shared by the plurality of image sensing elements, and deep trench isolation (DTI) structures extending from the shared ground node and between adjacent image sensing elements of the plurality of image sensing elements. The image sensor further includes a second chip bonded to the first chip and including a source follower, a reset transistor, a row select transistor, and an in-pixel circuit, where the source follower is electrically coupled to the diffusion wells. The image sensor further includes a third chip bonded to the second chip and including an application-specific circuit, where the application-specific circuit is electrically coupled to the in-pixel circuit.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a semiconductor substrate. A dielectric structure is disposed on a first side of the semiconductor substrate. An isolation structure extends from the dielectric structure into the first side of the semiconductor substrate. The isolation structure laterally wraps around the photodetector and comprises an upper portion disposed above the first side of the semiconductor substrate and directly contacting sidewalls of the dielectric structure. The isolation structure comprises a first material different from a second material of the dielectric structure.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The substrate comprises a front-side surface opposite a back-side surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the back-side surface toward the front-side surface. The inner isolation structure comprises a second height less than the first height.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a substrate having a first side and a second side. The substrate includes a pixel region. A photodetector is in the pixel region. A first doped region is in the pixel region. A second doped region is in the pixel region. The second doped region is vertically between the first doped region and the first side of the substrate. A doped well is in the substrate and laterally surrounds the pixel region. The doped well is partially in the second doped region. A portion of the second doped region is vertically between the doped well and the second side of the substrate. A trench isolation structure is in the semiconductor substrate and laterally surrounds the pixel region. A footprint of the trench isolation structure is within a footprint of the doped well.

Abstract: A first side of a sensor wafer is bonded to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation that enters the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer contains circuitry configured to operate the pixels. The sensor wafer or the first logic wafer contains a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. A through-substrate-via (TSV) is formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from being damaged during the forming of the TSV. The second side of the first logic wafer is bonded to a second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.

Abstract: A semiconductor device includes a first chip comprising a plurality of photo-sensitive devices, wherein the plurality of photo-sensitive devices are formed as a first array. The semiconductor device includes a second chip bonded to the first chip and comprising: a plurality of groups of pixel transistors, wherein the plurality of groups of pixel transistors are formed as a second array; and a plurality of input/output transistors, wherein the plurality of input/output transistors are disposed outside the second array. The semiconductor device includes a third chip bonded to the second chip and comprising a plurality of logic transistors.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip including a substrate having an upper surface vertically below a top surface. A dielectric structure contacts the top surface of the substrate. A conductive structure is disposed in the substrate. The conductive structure includes an upper conductive body and conductive protrusions directly underlying the upper conductive body. The upper conductive body overlies the upper surface of the substrate. A bottom surface of the dielectric structure is disposed between a top surface and a bottom surface of the upper conductive body. An isolation structure is disposed in the substrate on opposing sides of the upper conductive body.

Abstract: A cooling system for a rack of servers includes a plurality of cooling circuits, where each cooling circuit is coupled to a server of the rack. Each cooling circuit includes a plurality of cooling modules arranged in parallel. Each cooling module includes a cold plate having a cooling conduit passing therethrough, and a pump fluidly coupled to the cooling conduit. The cooling circuit further includes one or more valves fluidly interconnecting the plurality of cooling modules. Each of the one or more valves, when turned on, fluidly connects the cooling conduits of any two adjacent cooling modules. The cooling system further includes a first cooling distribution manifold fluidly connected to the cooling circuit of each of the plurality of servers through an inlet pipe, and a second cooling distribution manifold fluidly connected to the cooling circuit of each of the plurality of servers through an outlet pipe.

Abstract: According to one example, a device includes a semiconductor substrate. The device further includes a plurality of color filters disposed above the semiconductor substrate. The device further includes a plurality of micro-lenses disposed above the set of color filters. The device further includes a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses. The structure and the color filters are level at respective top surfaces and bottom surfaces thereof.

Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and has only a first gate dielectric thickness at a first IC chip at which a photodetector of the of the pixel sensor is arranged. Further, the pixel sensor has only one or more second gate dielectric thicknesses at a second IC chip that is stacked with the first IC chip, and the one or more second gate dielectric thicknesses is/are less than or equal to the first gate dielectric thickness. The first and second gate dielectric thicknesses correspond to transistors of the pixel sensor, which form a pixel circuit of the pixel sensor configured to facilitate readout of the photodetector.