Abstract: A semiconductor structure and its manufacturing method are provided. A semiconductor structure includes a substrate and several bit lines on the substrate. Each of the bit lines includes a first conductive layer on the substrate, a second conductive layer on the first conductive layer, and a hardmask layer on the second conductive layer. The semiconductor structure further includes several contacts disposed on the substrate and positioned between two adjacent bit lines, wherein the bottom surfaces of the contacts physically contact the substrate. The top surfaces of the contacts are not higher than the top surfaces of the hardmask layers. Each of the contacts includes a bottom contact part on the substrate and a top contact part on the bottom contact part, and a width of a top surface of the top contact part is greater than a width of a top surface of the bottom contact part.

Abstract: A manufacturing method for a memory structure including the following steps is provided. A bit line structure is formed on the substrate. A contact structure is formed on the substrate on one side of the bit line structure. A capacitor structure is formed on the contact structure. The capacitor structure includes a first electrode, a second electrode and an insulating layer. The first electrode is disposed on the contact structure in a misaligned manner. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is disposed on the contact structure. The second electrode is located on the first electrode. The insulating layer is disposed between the first electrode and the second electrode.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, and a capacitor structure is provided. The bit line structure is located on the substrate. The contact structure is located on the substrate on one side of the bit line structure. The capacitor structure is located on the contact structure. The capacitor structure includes a first electrode, a second electrode, and an insulating layer. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is only located on a part of the contact structure. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode.

Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.

Abstract: A method for manufacturing a semiconductor device includes forming contacts disposed in a dielectric layer. The method of forming the contacts includes forming contact holes and then filling with a conductive material. The method of forming the contact holes includes steps of forming openings in the dielectric layer to expose active regions, introducing a first oxygen plasma and a first fluorine plasma to remove by-products and oxidize inner surfaces of the openings, introducing a second oxygen plasma and a second fluorine plasma to remove the oxidized inner surfaces and repair the active regions, introducing a third oxygen plasma to oxidize inner surfaces again to form an oxide layer, and removing the oxide layer. The cross-sectional structure of two adjacent contact holes includes a capital, a base, and a shaft between the capital and the base, wherein the shaft has a smaller width than the base and the capital.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate having a plurality of active regions, at least one dielectric layer formed on the substrate, and a plurality of contacts disposed in the dielectric layer and contacting with the active regions. The contact is a barrel-shaped structure with a middle portion, a head portion having a perimeter small than that of the middle portion, and an end portion having a perimeter small than that of the middle portion.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, and a capacitor structure is provided. The bit line structure is located on the substrate. The contact structure is located on the substrate on one side of the bit line structure. The capacitor structure is located on the contact structure. The capacitor structure includes a first electrode, a second electrode, and an insulating layer. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is only located on a part of the contact structure. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode.

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Abstract: A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate having a plurality of active regions, at least one dielectric layer formed on the substrate, and a plurality of contacts disposed in the dielectric layer and contacting with the active regions. The contact is a barrel-shaped structure with a middle portion, a head portion having a perimeter small than that of the middle portion, and an end portion having a perimeter small than that of the middle portion.

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a plurality of gate structures, a plurality of dielectric structures, and spacers. The plurality of gate structures is disposed on the substrate. The plurality of dielectric structures is respectively disposed between the gate structures and the substrate, wherein a top width of the dielectric structure is less than the bottom width of the dielectric structure. The spacers are disposed on the sidewalls of the gate structures and cover the sidewalls of the dielectric structures.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: Provided is a method of manufacturing a DRAM. A plurality of openings are formed in the substrate. A hard mask is formed on the sidewall of an upper part of each opening. The substrate and the hard mask are partially removed to form a plurality of isolation trenches and to define active regions. Each active region is located between the isolation trenches and remaining portions of the hard mask are located on two sides of each active region. The isolation trenches and the openings are filled with a dielectric layer. The substrate and the dielectric layer are partially removed to form a plurality of buried word line trenches. Each buried word line trench extends along a third direction and passes through the active regions, the openings and the isolation trenches. A plurality of buried word lines are formed in the buried word line trenches.

Abstract: A semiconductor device is provided. The semiconductor device includes a core structure, a first pattern and a second pattern. The core structure is disposed on a substrate. The first pattern covers a sidewall of a bottom portion of the core structure. The top surface of the first pattern is lower than a top surface of the core structure. The second pattern is disposed on the first pattern and covering a top portion of the core structure. A sidewall of the top portion of the core structure and the top surface of the core structure are covered by the second pattern. The second pattern has an upper portion tapered away from the substrate. A material of the first pattern is different from a material of the second pattern.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.