Patents by Inventor Tzu-Ning Fang

Tzu-Ning Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7379317
    Abstract: A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: May 27, 2008
    Assignee: Spansion LLC
    Inventors: Colin S. Bill, Swaroop Kaza, Tzu-Ning Fang, Stuart Spitzer
  • Publication number: 20080112206
    Abstract: In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 15, 2008
    Inventors: Tzu-Ning Fang, Swaroop Kaza, An Chen, Sameer Haddad
  • Patent number: 7286388
    Abstract: In the present method of programming a memory device from an erased state, the memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes. In the programming method, (i) an electrical potential is applied across the first and second electrodes from higher to lower potential in one direction to reduce the resistance of the memory device, and (ii) an electrical potential is applied across the first and second electrodes from higher to lower potential in the other direction to further reduce the resistance of the memory device.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: October 23, 2007
    Assignee: Spansion LLC
    Inventors: An Chen, Sameer Haddad, Tzu-Ning Fang, Yi-Ching Jean Wu, Colin S. Bill
  • Patent number: 7273766
    Abstract: An organic memory device comprising two electrodes having a selectively conductive decay media between the two electrodes provides a capability to control a persistence level for information stored in an organic memory cell. A resistive state of the cell controls a conductive decay rate of the cell. A high and/or low resistive state can provide a fast and/or slow rate of conductive decay. One aspect of the present invention can have a high resistive state equating to an exponential conductive decay rate. Another aspect of the present invention can have a low resistive state equating to a logarithmic conductive decay rate. Yet another aspect relates to control of an organic memory device by determining a power state and setting a resistive state of an organic memory cell based upon a current power state and/or an imminent power state.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: September 25, 2007
    Assignee: Spansion LLC
    Inventors: Zhida Lan, Michael A. Van Buskirk, Tzu-Ning Fang, Colin Bill, John S. Ennals
  • Publication number: 20070025166
    Abstract: System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 1, 2007
    Applicant: SPANSION LLC
    Inventors: Tzu-Ning Fang, Colin Bill, Wei Cai, David Gaun, Eugen Gershon
  • Publication number: 20060256608
    Abstract: Provided herein is method of programming a resistive memory device, the resistive memory device including a first electrode, a second electrode, a passive layer between the first and second electrode, and an active layer between the first and second electrodes. In the programming method, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the active layer to the passive layer so that electronic charge carriers enter the active layer and are held by traps therein. In erasing the memory device, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the passive layer to the active layer so that electronic charge carriers are moved from the active layer.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 16, 2006
    Inventors: An Chen, Sameer Haddad, Tzu-Ning Fang
  • Publication number: 20060221713
    Abstract: A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Michael VanBuskirk, Colin Bill, Zhida Lan, Tzu-Ning Fang
  • Patent number: 7072781
    Abstract: A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eugen Gershon, David Gaun, Colin S. Bill, Tzu-Ning Fang
  • Publication number: 20060139994
    Abstract: A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 29, 2006
    Inventors: Colin Bill, Swaroop Kaza, Tzu-Ning Fang, Stuart Spitzer
  • Publication number: 20060113524
    Abstract: One aspect of the present invention relates to a semiconductor transistor device with an annular gate surrounding, at least in part, a channel that conducts current between a first and second source/drain. Another aspect of the present invention relates to a semiconductor transistor device having an annular gate and containing a channel composed of a polymer material. Yet another aspect of the present invention relates to fabrication of a device utilizing a polymer channel surrounded, at least in part, by an annular gate. Still yet another aspect of the present invention relates to a system with a means to control (and/or amplify) current via an annular gate surrounding a channel which conducts current between a first and second source/drain. Still other aspects of the present invention include devices incorporating the present invention's devices, systems and methods such as computers, memory, handhelds and electronic devices.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 1, 2006
    Inventors: Colin Bill, Michael Van Buskirk, Zhida Lan, John Ennals, Tzu-Ning Fang
  • Publication number: 20060104111
    Abstract: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor.
    Type: Application
    Filed: November 17, 2004
    Publication date: May 18, 2006
    Inventors: Nicholas Tripsas, Colin Bill, Michael VanBuskirk, Matthew Buynoski, Tzu-Ning Fang, Wei Cai, Suzette Pangrle, Steven Avanzino
  • Patent number: 7035141
    Abstract: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: April 25, 2006
    Inventors: Nicholas H. Tripsas, Colin S. Bill, Michael A. VanBuskirk, Matthew Buynoski, Tzu-Ning Fang, Wei Daisy Cai, Suzette Pangrle, Steven Avanzino
  • Publication number: 20060067105
    Abstract: Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.
    Type: Application
    Filed: November 8, 2004
    Publication date: March 30, 2006
    Applicant: Advanced Micro Devices, Inc
    Inventors: Tzu-Ning Fang, Michael Van Buskirk, Colin Bill
  • Patent number: 6943370
    Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 13, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan
  • Patent number: 6847047
    Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: January 25, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan
  • Publication number: 20040245522
    Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
    Type: Application
    Filed: June 30, 2004
    Publication date: December 9, 2004
    Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan
  • Publication number: 20040084743
    Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan