Patents by Inventor Tzu-Yen Hsieh
Tzu-Yen Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9123743Abstract: Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface.Type: GrantFiled: March 8, 2013Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Tzu-Yen Hsieh, Ming-Chia Tai, Chao-Cheng Chen
-
Publication number: 20150243504Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.Type: ApplicationFiled: May 14, 2015Publication date: August 27, 2015Inventors: Tzu-Yen HSIEH, Ming-Ching CHANG, Chun-Hung LEE, Yih-Ann LIN, De-Fang CHEN, Chao-Cheng CHEN
-
Patent number: 9111861Abstract: An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresist layer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresist layer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.Type: GrantFiled: February 6, 2012Date of Patent: August 18, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chia-Wei Chang, Chao-Cheng Chen, Chun-Hung Lee, Dai-Lin Wu
-
Patent number: 9059085Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, the patterned mask layer having a plurality of first features with a first pitch. The method includes patterning the material layer by using the patterned mask layer as a mask to form the first features in the material layer. The method includes trimming the patterned mask layer, after patterning the material layer, to form a trimmed patterned mask layer. The method further includes introducing a plurality of dopants into the material layer exposed by the trimmed patterned mask layer to form doped regions having a second pitch, wherein the second pitch is different from the first pitch. The method further includes removing the trimmed patterned mask layer to expose un-doped regions in the material layer; and removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions.Type: GrantFiled: June 13, 2014Date of Patent: June 16, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yen Hsieh, Chang Ming-Ching, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
-
Patent number: 9054125Abstract: A method for forming a semiconductor device includes forming a gate structure over a semiconductor substrate. The gate structure includes a gate electrode, at least two hard mask (HM) layers over the gate electrode, and a spacer abutting a side wall of the gate electrode and the at least two hard mask layers. The method further comprises forming a contact etch stop layer (CESL) over the gate structure, exposing at least one of the HM layers after forming the CESL, and removing the exposed at least one of the HM layers.Type: GrantFiled: April 30, 2013Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chung Wang, Tzu-Yen Hsieh
-
Publication number: 20140322872Abstract: A method for forming a semiconductor device includes forming a gate structure over a semiconductor substrate. The gate structure includes a gate electrode, at least two hard mask (HM) layers over the gate electrode, and a spacer abutting a side wall of the gate electrode and the at least two hard mask layers. The method further comprises forming a contact etch stop layer (CESL) over the gate structure, exposing at least one of the HM layers after forming the CESL, and removing the exposed at least one of the HM layers.Type: ApplicationFiled: April 30, 2013Publication date: October 30, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chung WANG, Tzu-Yen HSIEH
-
Patent number: 8853092Abstract: A method of fabricating a plurality of features of a semiconductor device includes providing a dielectric layer over a silicon layer, and etching the dielectric layer and the silicon layer to form a plurality of first apertures in the dielectric layer and the silicon layer, wherein adjacent apertures of the plurality of first apertures are set apart by a first pitch. The method further includes etching a plurality of second apertures in the dielectric layer, each aperture of the plurality of second apertures having a greater width than and centered about a respective aperture of the plurality of first apertures, implanting a plurality of dopants into the silicon layer aligned through the plurality of second apertures in the dielectric layer, wherein doped portions of the silicon layer are set apart by a second pitch less than the first pitch, and removing undoped portions of the silicon layer.Type: GrantFiled: December 30, 2011Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Tzu-Yen Hsieh
-
Publication number: 20140295654Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, the patterned mask layer having a plurality of first features with a first pitch. The method includes patterning the material layer by using the patterned mask layer as a mask to form the first features in the material layer. The method includes trimming the patterned mask layer, after patterning the material layer, to form a trimmed patterned mask layer. The method further includes introducing a plurality of dopants into the material layer exposed by the trimmed patterned mask layer to form doped regions having a second pitch, wherein the second pitch is different from the first pitch. The method further includes removing the trimmed patterned mask layer to expose un-doped regions in the material layer; and removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions.Type: ApplicationFiled: June 13, 2014Publication date: October 2, 2014Inventors: Tzu-Yen HSIEH, Chang MING-CHING, Chun-Hung LEE, Yih-Ann LIN, De-Fang CHEN, Chao-Cheng CHEN
-
Publication number: 20140284724Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.Type: ApplicationFiled: March 31, 2014Publication date: September 25, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
-
Publication number: 20140191308Abstract: A semiconductor device is provided. The semiconductor device includes a microelectronic layer, a first mask layer formed on the microelectronic layer having first features separated by first openings, and a second mask layer formed on the first mask layer having second features that are separated by second openings. Each second feature is centrally located on a respective one of the first features. A length each second feature in a dimension is substantially equal to a length of a respective one of the first openings in the dimension.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Spansion LLCInventor: Tzu-Yen HSIEH
-
Patent number: 8772183Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.Type: GrantFiled: October 20, 2011Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Chang Ming-Ching, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
-
Patent number: 8691655Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.Type: GrantFiled: May 15, 2012Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
-
Patent number: 8680671Abstract: A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.Type: GrantFiled: January 28, 2009Date of Patent: March 25, 2014Assignee: Spansion LLCInventor: Tzu-Yen Hsieh
-
Publication number: 20130309834Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.Type: ApplicationFiled: May 15, 2012Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
-
Publication number: 20130203247Abstract: An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yen HSIEH, Ming-Ching CHANG, Chia-Wei CHANG, Chao-Cheng CHEN, Chun-Hung LEE, Dai-Lin WU
-
Publication number: 20130187235Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Sheng Huang, Tzu-Yen Hsieh, Ming-Ching Chang, Chao-Cheng Chen, Chia-Jen Chen
-
Publication number: 20130171812Abstract: A method of fabricating a plurality of features of a semiconductor device includes providing a dielectric layer over a silicon layer, and etching the dielectric layer and the silicon layer to form a plurality of first apertures in the dielectric layer and the silicon layer, wherein adjacent apertures of the plurality of first apertures are set apart by a first pitch. The method further includes etching a plurality of second apertures in the dielectric layer, each aperture of the plurality of second apertures having a greater width than and centered about a respective aperture of the plurality of first apertures, implanting a plurality of dopants into the silicon layer aligned through the plurality of second apertures in the dielectric layer, wherein doped portions of the silicon layer are set apart by a second pitch less than the first pitch, and removing undoped portions of the silicon layer.Type: ApplicationFiled: December 30, 2011Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Tzu-Yen Hsieh
-
Publication number: 20130102136Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yen HSIEH, Chang MING-CHING, Chun-Hung LEE, Yih-Ann LIN, De-Fang CHEN, Chao-Cheng CHEN
-
Publication number: 20100187596Abstract: A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Applicant: Spansion LLCInventor: Tzu-Yen Hsieh
-
Patent number: 7279429Abstract: In one embodiment, the present invention relates to a method for increasing the ignition reliability of a plasma in a plasma reactor, the method comprising: supplying a source gas to the plasma reactor, the source gas comprising: (a) at least one reactive compound; and (b) at least one ignition gas, wherein the at least one ignition gas increases the ignitability of the source gas as compared to the ignitability of the source gas lacking the at least one ignition gas.Type: GrantFiled: October 1, 2004Date of Patent: October 9, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Calvin T. Gabriel, Tzu-Yen Hsieh