Abstract: A method of introducing dopants into a semiconductor wafer includes implanting the dopants into a region below a surface of the semiconductor wafer using an ion beam to form a first implanted layer. The dopants when activated causing a conductivity of the implanted layer to be either of N-type or P-type. The first implanted layer is characterized by a peak dopant concentration at a first depth below the surface of the semiconductor wafer. The method also includes removing a layer from the semiconductor wafer surface, wherein said layer includes a portion of said dopants.

Abstract: A method of introducing an impurity into a wafer surface is provided. The method comprises the steps of: low energy implantation of impurity into a surface of the wafer to generate an implanted dopant layer; and simultaneously removing an implanted surface of the implanted dopant layer to generate a doping profile with controlled areal impurity dosage.

Abstract: An apparatus for patterning objects for the manufacture of semiconductor integrated circuits includes an optical source, multiple fiber cores coupled to the optical source, each of the fiber cores has an input end and an output end, and each of the input ends is coupled to the optical source. The apparatus further includes an array coupled to each of the fiber cores, the array is configured to allow each of the fiber ends to output toward a common plane, an object having a photosensitive material coupled to the common plane, and a pattern that is exposed onto the photosensitive material. The pattern is composed of a number beams corresponding to a number of fiber cores.

Abstract: An apparatus for patterning objects for the manufacture of semiconductor integrated circuits includes an optical source, multiple fiber cores coupled to the optical source, each of the fiber cores has an input end and an output end, and each of the input ends is coupled to the optical source. The apparatus further includes an array coupled to each of the fiber cores, the array is configured to allow each of the fiber ends to output toward a common plane, an object having a photosensitive material coupled to the common plane, and a pattern that is exposed onto the photosensitive material. The pattern is composed of a number beams corresponding to a number of fiber cores.

Abstract: A method for patterning objects, e.g., semiconductor wafer, glass plate, composite, etc. The method includes providing an object, which has an overlying layer of photosensitive material. The method includes selectively applying light through one or more fiber cores from a plurality of fiber cores. Each of the fiber cores has an input end and an output end. Each of the input ends is coupled to the optical source. The plurality of fiber cores is numbered from 1 through N, where N is an integer greater than 1. Each of the output ends is also numbered from 1 through N, which corresponds respectively to each of the plurality of fiber cores numbered from 1 through N. The method exposes the photosensitive material from light emitted selectively through the one or more fiber cores. The one or more fiber cores out(s) light respectively through one or more output ends of the fiber cores. Each of the output ends numbered from 1 through N is associated with a pixel numbered respectively from 1 through N.

Abstract: A method for illuminating an object for selectively patterning a photosensitive material overlying the object using an array of mirror devices. The method includes applying electromagnetic radiation using a flood beam onto an array of mirror devices. Each of the mirror devices is associated with a pixel for a pattern to be exposed onto the photosensitive material. The method also includes selectively actuating one or more mirrors on the array to deflect corresponding portions of the beam onto corresponding portions of the photosensitive material to expose the portions of the photosensitive material on the object. The method maintains one or more other mirrors in a selected position(s) to maintain corresponding other portions of the photosensitive material free from exposure. Preferably, the combination of exposed and unexposed portions forms the pattern exposed onto the photosensitive material.

Abstract: A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon.

Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.

Abstract: A method for patterning objects, e.g., semiconductor wafer, glass plate, composite, etc. The method includes providing an object, which has an overlying layer of photosensitive material. The method includes selectively applying light through one or more fiber cores from a plurality of fiber cores. Each of the fiber cores has an input end and an output end. Each of the input ends is coupled to the optical source. The plurality of fiber cores is numbered from 1 through N, where N is an integer greater than 1. Each of the output ends is also numbered from 1 through N, which corresponds respectively to each of the plurality of fiber cores numbered from 1 through N. The method exposes the photosensitive material from light emitted selectively through the one or more fiber cores. The one or more fiber cores out(s) light respectively through one or more output ends of the fiber cores. Each of the output ends numbered from 1 through N is associated with a pixel numbered respectively from 1 through N.

Abstract: A method of introducing an impurity into a wafer surface is provided. The method comprises the steps of: low energy implantation of impurity into a surface of the wafer to generate an implanted dopant layer; and simultaneously removing an implanted surface of the implanted dopant layer to generate a doping profile with controlled areal impurity dosage.

Abstract: A method of identifying defect generating process of a plurality of lots of wafers in a manufacturing environment is provided, wherein each lots of the wafers are divided into a plurality of sub lots of wafers, and dividing all processes into groups of manufacturing stages, the method comprises the steps of: assigning all the sub lots a reference orientation to be processed in a first group of manufacturing stages; rotating one or more of sub lots by designated combination of rotational angles with respect to the reference orientation during each of the subsequent group of manufacturing stages; detecting a defect pattern of the sub lots, wherein the defect pattern corresponds to a rotational combination associated with the designated combination of rotational angles of the sub lots and the number of the plurality of sub lots; and identifying the group of manufacturing stages corresponding to the rotational combination.

Abstract: A reconfigurable mask for forming erasable patterns is disclosed. The mask includes material having optical properties manipulated by nonphysical means. In a preferred embodiment, the mask includes a liquid crystal array formed by materials that are transparent to the exposure light. A phase-shift mask can also be formed by controlling the refractive index of each cell. The mask can be used to form mask patterns that compensate for overexposure at corners of a mask pattern.

Abstract: A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation damage within active device regions. The method is particularly applicable to active device regions which have small lateral dimensions. Thus, the technological trend towards shrinking devices favors the incorporation of the process of the invention. The process utilizes a silicon nitride hardmask to define a narrow band around the perimeter of the device active area. A deep implant is performed through this mask, placing a ring of dopant below and outside the active area. The silicon nitride hardmask is then patterned a second time to define the conventional field oxide isolation regions. The LOCOS field oxidation is then performed whereby the implanted dopant diffuses vertically, engaging the field oxide around the perimeter of the device region and laterally filling in the region under the device active area.

Abstract: An inductor fabricated for semiconductor use is disclosed. The inductor is formed with a multi-level, multi-element conductor metallization structure which effectively increases conductance throughout the inductor thereby increasing the inductor's Q. The structure of the inductor may also provide for routing the current flowing through the multi-level, multi-element conductors in a way that increases the self inductance between certain conductive elements, thereby increasing the inductor's total inductance.

Abstract: An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls.

Abstract: A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. A first layer of polycrystalline material is deposited over the substrate and selectively removed such that only those portions of the polycrystalline layer that surround the stacks of material remain. A layer of silicon nitride or silicon dioxide is then formed over the substrate surface. A first resist is then spun on the substrate surface. This resist aggregates near the stacks of material. An isolation mask is generated that leaves exposed only those areas of the substrate that correspond to the area of overlap between the first polycrystalline area and the stacks of material, which also contain a layer of polycrystalline material.

Abstract: A novel process is disclosed for fabricating semiconductor devices with self-aligned contacts. Characteristic of the resulting structure is a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is prevented by interposing an insulating region therebetween.

Abstract: A new self-aligned contact technology is afforded by semiconductor devices having a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is afforded by interposing an insulating region therebetween.

Abstract: A novel fabrication method is disclosed for fabricating a bipolar transistor having a digitated emitter electrode and a contiguous polysilicon region acting as a self-aligned base contact. The process substantially reduces the parasitic capacitances as well as eliminates the need for the intrinsic base region to be exposed to multiple etching, which results in the fabrication of small and reproducible base widths.A first polysilicon layer is deposited over the surface of a semiconductor substrate and, then, implanted with base dopants, which are driven into the surface of the active region by a furnace process for forming an intrinsic base region. Emitter dopants are next implanted into the first polysilicon layer. Subsequently, a nitride layer is deposited and the digitated emitter fingers patterned by selective etching.

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks.