Patents by Inventor Tzu-Yu Wang
Tzu-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176093Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240077349Abstract: A server includes a chassis, an air duct, a sensing module and a board management controller. The air duct is disposed in the chassis. The sensing module is disposed in the chassis. The sensing module senses whether the air duct is correctly installed. The board management controller is disposed in the chassis and coupled to the sensing module. When the air duct is not correctly installed, the sensing module notifies the board management controller to generate a warning message.Type: ApplicationFiled: October 3, 2022Publication date: March 7, 2024Applicant: Wiwynn CorporationInventors: Po-Sheng Su, Ching-Wen Hsiao, Hsien-Yu Wang, Tzu-Shun Wang
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Patent number: 11682593Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: GrantFiled: July 20, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 11274957Abstract: An analytical system includes a laser disposed to direct light toward a microfluidic feature disposed in a feature layer of a multiple layer test cartridge, a sensor to receive reflections from capping layers disposed about the microfluidic feature in the feature layer, and a controller to determine a depth of the microfluidic feature as a function of the received reflections.Type: GrantFiled: October 16, 2018Date of Patent: March 15, 2022Assignee: Honeywell International Inc.Inventor: Tzu-Yu Wang
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Publication number: 20200350221Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 10734295Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: GrantFiled: October 1, 2018Date of Patent: August 4, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Publication number: 20190057912Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: ApplicationFiled: October 1, 2018Publication date: February 21, 2019Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Publication number: 20190049285Abstract: An analytical system includes a laser disposed to direct light toward a microfluidic feature disposed in a feature layer of a multiple layer test cartridge, a sensor to receive reflections from capping layers disposed about the microfluidic feature in the feature layer, and a controller to determine a depth of the microfluidic feature as a function of the received reflections.Type: ApplicationFiled: October 16, 2018Publication date: February 14, 2019Inventor: Tzu-Yu Wang
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Patent number: 10139263Abstract: An analytical system includes a laser disposed to direct light toward a microfluidic feature disposed in a feature layer of a multiple layer test cartridge, a sensor to receive reflections from capping layers disposed about the microfluidic feature in the feature layer, and a controller to determine a depth of the microfluidic feature as a function of the received reflections.Type: GrantFiled: March 11, 2013Date of Patent: November 27, 2018Assignee: Honeywell International Inc.Inventor: Tzu-Yu Wang
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Patent number: 10090213Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: GrantFiled: March 3, 2017Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 10054938Abstract: A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity.Type: GrantFiled: May 7, 2015Date of Patent: August 21, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung Cheng Ko, Tzu-Yu Wang, Kewei Zuo, Kuan Teng Lo, Chien Rhone Wang, Chih-Wei Lai
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Patent number: 10056347Abstract: A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.Type: GrantFiled: January 23, 2017Date of Patent: August 21, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Tzu-Wei Chiu, Tzu-Yu Wang, Shang-Yun Hou, Shin-Puu Jeng, Hsien-Wei Chen, Hung-An Teng, Wei-Cheng Wu
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Patent number: 9760670Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.Type: GrantFiled: June 6, 2016Date of Patent: September 12, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Wang, Wei-Cheng Wu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 9691840Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.Type: GrantFiled: December 18, 2013Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: An-Jhih Su, Chi-Chun Hsieh, Tzu-Yu Wang, Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
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Publication number: 20170178983Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Publication number: 20170133346Abstract: A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.Type: ApplicationFiled: January 23, 2017Publication date: May 11, 2017Inventors: Tzu-Wei Chiu, Tzu-Yu Wang, Shang-Yun Hou, Shin-Puu Jeng, Hsien-Wei Chen, Hung-An Teng, Wei-Cheng Wu
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Patent number: 9588505Abstract: Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.Type: GrantFiled: April 25, 2013Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Wang, Chen-Hua Yu, Chien Rhone Wang, Henry Lo, Jung Cheng Ko, Chih-Wei Lai, Kewei Zuo
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Patent number: 9589857Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: GrantFiled: September 4, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng