Patents by Inventor Tzung-Han Tan
Tzung-Han Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9905711Abstract: An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the back side of the substrate.Type: GrantFiled: April 15, 2016Date of Patent: February 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tzung-Han Tan, Chang-Sheng Hsu, Meng-Jia Lin, Te-Huang Chiu
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Publication number: 20170271529Abstract: An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the back side of the substrate.Type: ApplicationFiled: April 15, 2016Publication date: September 21, 2017Inventors: Tzung-Han Tan, Chang-Sheng Hsu, Meng-Jia Lin, Te-Huang Chiu
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Patent number: 9150407Abstract: A method for fabricating a microelectromechanical system (MEMS) device of the present invention includes the following steps: providing a substrate, comprising a circuit region and a MEMS region separated from each other; forming an interconnection structure on the substrate in the circuit region, and simultaneously forming a plurality of dielectric layers and a first electrode on the substrate in the MEMS region, wherein the first electrode comprises at least two metal layers formed in the dielectric layers and a protection ring formed in the dielectric layers and connecting two adjacent metal layers, so as to define an enclosed space between the two adjacent metal layers; forming a second electrode on the first electrode; and removing the dielectric layers outside the enclosed space in the MEMS region to form a cavity between the electrodes.Type: GrantFiled: July 18, 2013Date of Patent: October 6, 2015Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang, Meng-Jia Lin
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Patent number: 8865500Abstract: A method of fabricating a MEMS microphone includes: first providing a substrate having a first surface and a second surface. The substrate is divided into a logic region and a MEMS region. The first surface of the substrate is etched to form a plurality of first trenches in the MEMS region. An STI material is then formed in the plurality of first trenches. Subsequently, the second surface of the substrate is etched to form a second trench in the MEMS region, wherein the second trench connects with each of the first trenches. Finally, the STI material in the first trenches is removed.Type: GrantFiled: February 3, 2010Date of Patent: October 21, 2014Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan
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Patent number: 8710601Abstract: A micro electro mechanical system (MEMS) structure is disclosed. The MEMS structure includes a backplate electrode and a 3D diaphragm electrode. The 3D diaphragm electrode has a composite structure so that a dielectric is disposed between two metal layers. The 3D diaphragm electrode is adjacent to the backplate electrode to form a variable capacitor together.Type: GrantFiled: November 19, 2009Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Min Chen, Meng-Jia Lin
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Patent number: 8642986Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.Type: GrantFiled: September 23, 2009Date of Patent: February 4, 2014Assignee: United Microelectronics Corp.Inventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Tzung-I Su, Chien-Hsin Huang, Hui-Min Wu, Chao-An Su, Min Chen, Meng-Jia Lin
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Patent number: 8587078Abstract: A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.Type: GrantFiled: April 6, 2010Date of Patent: November 19, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Tzung-I Su
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Publication number: 20130302933Abstract: A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The method of the present invention includes the following steps. A substrate is provided, including a circuit region and a MEMS region separated from each other. An interconnection structure is formed on the substrate in the circuit region, and simultaneously a plurality of dielectric layers and a first electrode are formed on the substrate in the MEMS region. The first electrode includes at least two metal layers and a protection ring. The metal layers and the protection ring are formed in the dielectric layers. The protection ring connects two adjacent metal layers, so as to define an enclosed space between the two adjacent metal layers. A second electrode is formed on the first electrode. The dielectric layers outside the enclosed space in the MEMS region are removed to form a cavity between the electrodes.Type: ApplicationFiled: July 18, 2013Publication date: November 14, 2013Inventors: Tzung-Han TAN, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang, Meng-Jia Lin
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Patent number: 8558336Abstract: A semiconductor photodetector structure is provided. The structure includes a substrate, a photodetecting element and a semiconductor layer disposed on the photodetecting element. The substrate includes a first semiconductor material and includes a deep trench. The surface of the deep trench includes a first type dopant. The photodetecting element is disposed in the deep trench. The photodetecting element includes a second semiconductor material. The semiconductor layer includes a second type dopant.Type: GrantFiled: August 17, 2009Date of Patent: October 15, 2013Assignee: United Microelectronics Corp.Inventors: Tzung-I Su, Bang-Chiang Lan, Chao-An Su, Hui-Min Wu, Ming-I Wang, Chien-Hsin Huang, Tzung-Han Tan, Min Chen, Meng-Jia Lin, Wen-Yu Su
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Patent number: 8525389Abstract: A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The MEMS device includes a first electrode and a second electrode. The first electrode is disposed on a substrate, and includes at least two metal layers, a first protection ring and a dielectric layer. The first protection ring connects two adjacent metal layers, so as to define an enclosed space between two adjacent metal layers. The dielectric layer is disposed in the enclosed space and connects two adjacent metal layers. The second electrode is disposed on the first electrode, wherein a cavity is formed between the first electrode and the second electrode.Type: GrantFiled: November 10, 2010Date of Patent: September 3, 2013Assignee: United Microelectronics Corp.Inventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang, Meng-Jia Lin
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Patent number: 8502382Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.Type: GrantFiled: April 30, 2012Date of Patent: August 6, 2013Assignee: United Microelectronics Corp.Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
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Patent number: 8384214Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure.Type: GrantFiled: October 13, 2009Date of Patent: February 26, 2013Assignee: United Microelectronics Corp.Inventors: Hui-Min Wu, Bang-Chiang Lan, Ming-I Wang, Tzung-I Su, Chien-Hsin Huang, Chao-An Su, Tzung-Han Tan, Min Chen, Meng-Jia Lin
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Patent number: 8299555Abstract: A method of fabricating a semiconductor optoelectronic structure is provided. First, a substrate is provided, and a waveguide is formed therein, and then a plurality of dielectric layers is formed on the waveguide. Next, a contact pad and a passivation layer are provided on the dielectric layers and a patterned mask layer is formed thereon. Last, an etching process is provided by using the patterned mask layer to expose the contact pad and remove a portion of the passivation layer and the dielectric layers to form a transformer.Type: GrantFiled: November 15, 2009Date of Patent: October 30, 2012Assignee: United Microelectronics Corp.Inventors: Tzung-I Su, Chao-An Su, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Chien-Hsin Huang, Min Chen, Meng-Jia Lin
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Publication number: 20120205808Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.Type: ApplicationFiled: April 30, 2012Publication date: August 16, 2012Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
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Patent number: 8208768Abstract: A focusing member and an optoelectronic device having the same are provided. The focusing member includes multiple levels of conductive plugs and multiple levels of conductive layers that together form an inversed half-boat shape. The optoelectronic device includes a bottom layer, an optical waveguide above the bottom layer, a dielectric layer covering the optical waveguide, and the above focusing member disposed at an edge of the optoelectronic device and located in the dielectric layer above the optical waveguide. A wider end of the inversed half-boat shape of the focusing member faces the outside of the optoelectronic device. The refractive indexes of the bottom layer and the dielectric layer are smaller than that of the optical waveguide.Type: GrantFiled: October 26, 2009Date of Patent: June 26, 2012Assignee: United Microelectronics Corp.Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Hui-Min Wu, Chien-Hsin Huang, Tzung-Han Tan, Min Chen, Meng-Jia Lin
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Patent number: 8193640Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.Type: GrantFiled: August 10, 2009Date of Patent: June 5, 2012Assignee: United Microelectronics Corp.Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
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Patent number: 8139907Abstract: An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the first area. The refractive index of the half-boat-shaped material layer is lower than that of the substrate. A top surface of the half-boat-shaped material layer is coplanar with the surface of the substrate. The deep trench isolation structure is disposed in the substrate within the first area and located at one side of a bow portion of the half-boat-shaped material layer. The optical waveguide is disposed on the substrate within the first area. The optical waveguide overlaps a portion of the deep trench isolation structure and at least a portion of the half-boat-shaped material layer.Type: GrantFiled: December 29, 2009Date of Patent: March 20, 2012Assignee: United Microelectronics Corp.Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Chien-Hsin Huang, Hui-Min Wu, Tzung-Han Tan, Min Chen, Meng-Jia Lin
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Publication number: 20110241137Abstract: A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.Type: ApplicationFiled: April 6, 2010Publication date: October 6, 2011Inventors: Chien-Hsin HUANG, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Tzung-I Su
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Publication number: 20110189804Abstract: A method of fabricating a MEMS microphone includes: first providing a substrate having a first surface and a second surface. The substrate is divided into a logic region and a MEMS region. The first surface of the substrate is etched to form a plurality of first trenches in the MEMS region. An STI material is then formed in the plurality of first trenches. Subsequently, the second surface of the substrate is etched to form a second trench in the MEMS region, wherein the second trench connects with each of the first trenches. Finally, the STI material in the first trenches is removed.Type: ApplicationFiled: February 3, 2010Publication date: August 4, 2011Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan
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Publication number: 20110158581Abstract: An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the first area. The refractive index of the half-boat-shaped material layer is lower than that of the substrate. A top surface of the half-boat-shaped material layer is coplanar with the surface of the substrate. The deep trench isolation structure is disposed in the substrate within the first area and located at one side of a bow portion of the half-boat-shaped material layer. The optical waveguide is disposed on the substrate within the first area. The optical waveguide overlaps a portion of the deep trench isolation structure and at least a portion of the half-boat-shaped material layer.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tzung-I Su, Ming-I Wang, Bang-Chiang Lan, Te-Kan Liao, Chao-An Su, Chien-Hsin Huang, Hui-Min Wu, Tzung-Han Tan, Min Chen, Meng-Jia Lin