Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Abstract: A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.

Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Abstract: An analog-to-digital (A/D) conversion device is provided and includes a first A/D conversion stage. The A/D conversion stage includes a first pre-amp unit, first and second latch units, and a first conversion unit. The first pre-amp unit amplifies the analog input data and outputs a first amplified data. The first and second latch units are enabled by first and second latch clock signals to latch the first and second amplified data and generate first and second latched data, respectively. The first pre-amp unit is reset between a time point when the first latch unit is enabled and a time point when the second latch unit is enabled. The first conversion unit receives the analog input data, and the first and second latched data and accordingly generates a first analog output data.

Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein all switches included in the OP-amp input switch block are implemented utilizing PMOS transistors only, and the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein all switches included in the OP-amp input switch block are implemented utilizing PMOS transistors only, and the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.

Abstract: An analog-to-digital (A/D) conversion device is provided and includes a first A/D conversion stage. The A/D conversion stage includes a first pre-amp unit, first and second latch units, and a first conversion unit. The first pre-amp unit amplifies the analog input data and outputs a first amplified data. The first and second latch units are enabled by first and second latch clock signals to latch the first and second amplified data and generate first and second latched data, respectively. The first pre-amp unit is reset between a time point when the first latch unit is enabled and a time point when the second latch unit is enabled. The first conversion unit receives the analog input data, and the first and second latched data and accordingly generates a first analog output data.

Abstract: A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.

Abstract: A high-to-low level shifter is disclosed, comprising a high voltage unit and a low voltage unit. The high voltage unit receives an input signal from an input node. The high voltage unit outputs a first output signal to an output node when the high voltage unit receives a low-voltage-level input signal. The low voltage unit outputs a second output signal to the output node when the high voltage unit receives a high-voltage-level input signal.

Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: A power-on reset circuit and method for generating a reset signal according to the voltage of a power source. The circuit includes an oscillator for generating an oscillation signal. The frequency of the oscillation signal increases with the rising of the voltage of the power source. The circuit further includes a frequency detector for converting the oscillation frequency of the oscillation signal into a first output voltage, and includes a reset signal output circuit for outputting a reset signal according to the first output voltage. Therefore, the power-on reset circuit can be applied in low-voltage chips.

Abstract: A fast start-up low-voltage bandgap voltage reference circuit is disclosed. The bandgap voltage reference circuit includes: a first current generator, which is implemented by a self-bias unit and a current mirror for generating a first reference current with positive temperature coefficient; a second current generator, which is connected to a point with negative temperature coefficient in the first current generator to generate a second reference current with negative temperature coefficient; and a resistor for converting the first reference current and the second reference current into a low-voltage bandgap voltage independent of temperature. Because the bandgap voltage reference circuit of the invention uses the resistor to convert the first reference current and the second reference current into voltage, the circuit can provide low-voltage bandgap voltage.

Abstract: The present invention discloses an impedance matching circuit which is suitable to be applied on an IC chip. The impedance matching circuit comprises a resistor unit, an OP amplifier circuit connected with the resistor unit, a feedback selecting circuit connected in parallel with the OP amplifier circuit, and a resistor selecting circuit connected with both the OP amplifier circuit and the feedback selecting circuit. The feedback selecting circuit further includes a plurality of switching circuits for enabling some of the resistors furnished in the resistor selecting circuit. By selecting and actuating one of the switching circuits, some certain resistors will be enabled so as to adjust the resistance value of the resistor selecting circuit. The resistor unit and the switching circuits are designed in such a manner that the resistor unit is able to compensate an equivalent resistance of the switching circuit which is actuated.

Abstract: A power-on reset circuit and method for generating a reset signal according to the voltage of a power source. The circuit includes an oscillator for generating an oscillation signal. The frequency of the oscillation signal increases with the rising of the voltage of the power source. The circuit further includes a frequency detector for converting the oscillation frequency of the oscillation signal into a first output voltage, and includes a reset signal output circuit for outputting a reset signal according to the first output voltage. Therefore, the power-on reset circuit can be applied in low-voltage chips.

Abstract: The present invention discloses an impedance matching circuit which is suitable to be applied on an IC chip. The impedance matching circuit comprises a resistor unit, an OP amplifier circuit connected with the resistor unit, a feedback selecting circuit connected in parallel with the OP amplifier circuit, and a resistor selecting circuit connected with both the OP amplifier circuit and the feedback selecting circuit. The feedback selecting circuit further includes a plurality of switching circuits for enabling some of the resistors furnished in the resistor selecting circuit. By selecting and actuating one of the switching circuits, some certain resistors will be enabled so as to adjust the resistance value of the resistor selecting circuit. The resistor unit and the switching circuits are designed in such a manner that the resistor unit is able to compensate an equivalent resistance of the switching circuit which is actuated.

Abstract: A fast start-up low-voltage bandgap voltage reference circuit is proposed. The bandgap voltage reference circuit comprises: a first current generator, which is implemented by a self-bias unit and a current mirror for generating a first reference current with positive temperature coefficient; a second current generator, which is connected to a point with negative temperature coefficient in the first current generator to generate a second reference current with negative temperature coefficient; and a resister for converting the first reference current and the second reference current into a low-voltage bandgap voltage independent of temperature. Because the bandgap voltage reference circuit of the invention uses the resistor to convert the first reference current and the second reference current into voltage, the circuit can provide low-voltage bandgap voltage.