Abstract: A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material.

Abstract: A method of automatically coupling between a fiber and an optical waveguide is disclosed. Such a scheme is achieved by the property of the different etching rate in the various wafer direction on a semiconductor material, especial silicon, and the shrinking property of the glass soot formed by a flame hydrolysis deposition technique during a high temperature consolidation process, for improving aligning accuracy. The manufacturing process of the method is described below. First, a waveguide buffer layer is formed on a semiconductor substrate, then a waveguide layer is formed on the semiconductor substrate and the waveguide buffer layer. A part of the waveguide is manipulated to the planar optical waveguide, meanwhile, several windows which lead to the I/O end of the planar waveguide are formed on the other waveguide layer. The semiconductor substrate beneath the windows is etched anisotropically to form several aligning grooves.

Abstract: A method for fabricating microelectromechanical systems containing a glass diaphragm formed on a silicon macrostructure is disclosed. The method comprises the steps of: (a) obtaining a silicon wafer and forming a cavity in the silicon wafer; (b) using a flame hydrolysis deposition technique to deposite glass soot into the cavity, the glass soot fills the cavity and extends onto the external surface of the silicon wafer so as to form a glass soot layer having a predetermined thickness; and (c) heat-consolidating the glass soot at temperatures between 850.degree. and 1,350.degree. C. so as to cause the glass soot to shrink and form a glass diaphragm over the cavity. The shrinkage ratio between the glass diaphragm and the glass soot layer is between 1:20 to 1:50. The silicon wafer can be further fabricated to contain a diaphragm-sealed cavity and/or a diaphragm-converted cantilever.

Abstract: A method for fabricating planar lightwave circuits with at least one static-alignment fiber-guiding groove comprising the steps of: (a) fabricating a sandwiched Si-substrate by forming an etching stop layer on a first Si layer, followed by forming a second Si layer on the etching stop layer; (b) forming a waveguide layer on the Si-substrate, the waveguide layer containing at least one planar waveguide channel buried between a first cladding layer and a second cladding layer; (c) forming a photomask on the waveguide layer so as to allow the fiber-guiding grooves to be fabricated; (d) using the photomask and a first reactive ion etching procedure to form a first portion of the fiber-guiding groove, the first reactive ion etching procedure is controlled such that it etches through the waveguide layer and stops at the second Si layer; and (e) using the photomask and a second reactive ion etching procedure to form a second portion of the fiber-guiding groove, wherein the second reactive etching ion is selected in