Abstract: An integrated circuit structure includes a substrate, semiconductor devices, an inter-layer dielectric (ILD) structure, an interconnect, a dielectric layer, an etching barrier layer, a conductive layer, and memory units. The semiconductor devices are on the substrate. The ILD structure is over the semiconductor devices. The interconnect is in the ILD structure and electrically connected to the semiconductor devices. The dielectric layer is over the ILD structure. The etching barrier layer is on the first dielectric layer. The conductive layer is on the etching barrier layer. The memory units are stacked in a vertical direction over the etching barrier layer.

Abstract: A semiconductor device includes a circuit board, a bottom plate, landing pads, a stack, support pillars, and memory pillars. The circuit board includes circuit structures and wires and has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed on the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and includes conductive layers and insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction and extend to the landing pads in the staircase area. The memory pillars pass through the stack along the first direction in the array area.

Abstract: Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.

Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

Abstract: A three-dimensional memory device and a method of manufacturing a three-dimensional memory device are provided. The method includes providing a precursor structure including a substrate, a multi-layered stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are then formed in the multi-layered stack and the substrate along a first direction, in which the first slit and the second slit have a pitch between thereof, and the second slit cuts the barrier structure. A portion of the second insulating layers is then replaced with a plurality of conductive layers. A first slit structure and a second slit structure are then formed in the first slit and the second slit, in which the first slit structure and the second slit structure separate the vertical channel pillars in a second direction that is different from the first direction.

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.

Abstract: An embodiment of the present the disclosure provides a memory device, including: a substrate, an interconnection structure disposed on the substrate, a conductive layer disposed on the interconnection structure, a stop layer disposed on the conductive layer, and a gate stack structure disposed on the stop layer. The gate stack structure includes a plurality of insulating layers and a plurality of gate conductive layers that alternate with each other. A ratio of a thickness of a bottommost insulating layer of the gate stack structure to a thickness of the stop layer is 1:1 to 1:2. The memory device further includes a channel pillar extending through the gate stack structure and the stop layer and to electrically connect the conductive layer, and a charge storage structure disposed between sidewalls of the channel pillar and the plurality of gate conductive layers.

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.

Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.

Abstract: Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.

Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

Abstract: A three-dimensional memory device and a method of manufacturing a three-dimensional memory device are provided. The method includes providing a precursor structure including a substrate, a multi-layered stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are then formed in the multi-layered stack and the substrate along a first direction, in which the first slit and the second slit have a pitch between thereof, and the second slit cuts the barrier structure. A portion of the second insulating layers is then replaced with a plurality of conductive layers. A first slit structure and a second slit structure are then formed in the first slit and the second slit, in which the first slit structure and the second slit structure separate the vertical channel pillars in a second direction that is different from the first direction.

Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.

Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.

Abstract: Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.

Abstract: Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.