Patents by Inventor Tzung-Yi Tsai
Tzung-Yi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136222Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).Type: ApplicationFiled: December 18, 2023Publication date: April 25, 2024Inventors: Tzung-Yi TSAI, Tsung-Lin LEE, Yen-Ming CHEN
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Patent number: 11948531Abstract: A light source device, including a first light source, providing a first light beam in a first time period of a first period; and a second light source, providing a second light beam in a second time period of the first period, is provided. The first light beam and the second light beam have the same color temperature. The first light beam and the second light beam are emitted alternately in the first period, and a color rendering index of mixed light of the first light beam and the second light beam is greater than or equal to 85.Type: GrantFiled: December 30, 2021Date of Patent: April 2, 2024Assignee: Industrial Technology Research InstituteInventors: Tzung-Te Chen, Hsin-Yun Tsai, Shih-Yi Wen, Chia-Fen Hsieh
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Publication number: 20240072079Abstract: A method for forming an isolation structure includes following operations. A trench is formed in a semiconductor substrate. A first insulating layer covering a bottom and sidewalls of the trench is formed. A charge-trapping layer is formed on the first insulating layer. The trench is filled with a second insulating layer. The charge-trapping layer include a material different from those of the first insulating layer and the second insulating layer.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Inventors: TZUNG-YI TSAI, KUO-YU WU, TSE-HUA LU
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Patent number: 11848230Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).Type: GrantFiled: August 9, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
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Patent number: 11848339Abstract: A semiconductor structure includes a semiconductor substrate, an image sensor, and an isolation structure. The isolation structure is adjacent to the image sensor and disposed in the semiconductor substrate. The isolation structure includes a first oxide layer, a second oxide layer over the first oxide layer, and a charge-trapping layer disposed between the first oxide layer and the second oxide layer. The charge-trapping layer includes a material different from those of the first oxide layer and the second oxide layer.Type: GrantFiled: March 19, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tzung-Yi Tsai, Kuo-Yu Wu, Tse-Hua Lu
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Patent number: 11569130Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.Type: GrantFiled: September 24, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
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Publication number: 20230017723Abstract: A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: MING-SHIANG LIN, TZUNG-YI TSAI, WAN-LIN CHIANG, HONG-PING LUO, KUO-YU WU, TSE-HUA LU
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Publication number: 20220359509Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Tsung-Chieh Hsiao, Johnson Chen, Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
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Publication number: 20220302190Abstract: A semiconductor structure includes a semiconductor substrate, an image sensor, and an isolation structure. The isolation structure is adjacent to the image sensor and disposed in the semiconductor substrate. The isolation structure includes a first oxide layer, a second oxide layer over the first oxide layer, and a charge-trapping layer disposed between the first oxide layer and the second oxide layer. The charge-trapping layer includes a material different from those of the first oxide layer and the second oxide layer.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Inventors: TZUNG-YI TSAI, KUO-YU WU, TSE-HUA LU
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Patent number: 11437372Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.Type: GrantFiled: July 24, 2020Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Chieh Hsiao, Johnson Chen, Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
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Publication number: 20220238350Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
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Patent number: 11302535Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.Type: GrantFiled: October 12, 2018Date of Patent: April 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
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Publication number: 20210366767Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
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Patent number: 11088022Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).Type: GrantFiled: February 14, 2019Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
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Publication number: 20210098451Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.Type: ApplicationFiled: July 24, 2020Publication date: April 1, 2021Inventors: Tsung-Chieh Hsiao, Johnson Chen, Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
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Publication number: 20210020517Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzung-Yi TSAI, Yen-Ming CHEN, Tsung-Lin LEE, Chih-Chieh YEH
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Patent number: 10811318Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.Type: GrantFiled: December 30, 2019Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
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Publication number: 20200144126Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.Type: ApplicationFiled: December 30, 2019Publication date: May 7, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzung-Yi TSAI, Yen-Ming CHEN, Tsung-Lin LEE, Chih-Chieh YEH
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Publication number: 20200105589Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).Type: ApplicationFiled: February 14, 2019Publication date: April 2, 2020Inventors: Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
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Publication number: 20200006084Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.Type: ApplicationFiled: October 12, 2018Publication date: January 2, 2020Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho