Patents by Inventor Tzungren Allan Tzeng
Tzungren Allan Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140244900Abstract: A memory module includes an input/output (I/O) interface adapted to fit into a system random access memory (RAM) socket. The module also includes at least one controller coupled to the I/O interface, the controller comprising a plurality of registers, and a plurality of non-volatile memory devices coupled to the controller. In the module, when data is received at the I/O interface, the received data is stored using at least one of the plurality of registers and the controller performs one of a plurality of non-volatile memory operations on at least a portion of the plurality of non-volatile memory devices based on the received data.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Inventors: Tzungren Allan Tzeng, Jan Silverman
-
Publication number: 20140229661Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: SPANSION LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8756376Abstract: A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: August 21, 2012Date of Patent: June 17, 2014Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8745311Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: GrantFiled: March 31, 2008Date of Patent: June 3, 2014Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8738840Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: GrantFiled: March 31, 2008Date of Patent: May 27, 2014Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8560761Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: GrantFiled: March 31, 2008Date of Patent: October 15, 2013Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8458393Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: GrantFiled: March 31, 2008Date of Patent: June 4, 2013Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8352671Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: February 5, 2008Date of Patent: January 8, 2013Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Publication number: 20120317348Abstract: A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Applicant: SPANSION LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8332572Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: February 5, 2008Date of Patent: December 11, 2012Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8275945Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: February 5, 2008Date of Patent: September 25, 2012Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 8209463Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: February 5, 2008Date of Patent: June 26, 2012Assignee: Spansion LLCInventor: Tzungren Allan Tzeng
-
Patent number: 7733130Abstract: A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal. The system includes circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched. Data is only latched when the pulse is asserted and on a given edge of the first clock signal, and the circuitry is configured to generate the pulse such that the given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal.Type: GrantFiled: March 6, 2008Date of Patent: June 8, 2010Assignee: Oracle America, Inc.Inventors: Mahmudul Hassan, Tzungren Allan Tzeng
-
Publication number: 20090248958Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: SPANSION LLCInventor: Tzungren Allan Tzeng
-
Publication number: 20090248957Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: SPANSION LLCInventor: Tzungren Allan Tzeng
-
Publication number: 20090249015Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: SPANSION LLCInventor: Tzungren Allan Tzeng
-
Publication number: 20090248959Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: Spansion LLCInventor: Tzungren Allan Tzeng
-
Publication number: 20090225915Abstract: A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal. The system includes circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched. Data is only latched when the pulse is asserted and on a given edge of the first clock signal, and the circuitry is configured to generate the pulse such that the given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal.Type: ApplicationFiled: March 6, 2008Publication date: September 10, 2009Inventors: Mahmudul Hassan, Tzungren Allan Tzeng
-
Publication number: 20090198872Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: ApplicationFiled: February 5, 2008Publication date: August 6, 2009Applicant: SPANSION LLCInventor: Tzungren Allan Tzeng
-
Publication number: 20090198873Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: ApplicationFiled: February 5, 2008Publication date: August 6, 2009Applicant: Spansion LLCInventor: Tzungren Allan Tzeng