Abstract: A circuit for ensuring stabilized configuration information upon power-up is disclosed. In one embodiment, a semiconductor device includes a configuration information stored in a number of nonvolatile storage elements (fuse bits (16)). A configuration power-on reset circuit (10) generates a signal for latching the configuration data into volatile configuration registers (18) on power-up. The configuration data signals are generated in response to a power-on reset (POR) pulse, and not latched until a predetermined delay after the POR pulse is terminated. The predetermined delay allows time for the data signals from the fuse bits (16) to “settle.” Subsequent POR pulses will not result in another latching action.