Abstract: A frequency compensated operational amplifier includes: an input stage, for receiving an input signal; an output stage, coupled to the input stage, for generating an output signal according to an output of the input stage; a first current source, for providing a first bias current; a second current source, for providing a second bias current identical to the first bias current; an Ahuja compensation circuit, comprising: a matched transistor pair, coupled to the first current source and the second current source; a capacitor coupled between the matched transistor pair and the output stage; and a transconductance boosting circuit, coupled to the matched transistor pair, for boosting transconductance of the matched transistor pair.

Abstract: A driving amplifier circuit includes: a first driver for souring a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) coupled to a differential input signal for driving the first driver; a second operational amplifier coupled to the differential input signal for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit, coupled to the first bias circuit and the second bias circuit, for enabling either the first bias circuit or the second bias circuit according to a control signal; and a digital control circuit, coupled to the enabling circuit, for monitoring currents of the first driver and the second driver to generate the control signal.

Abstract: A frequency compensated operational amplifier includes: an input stage, for receiving an input signal; an output stage, coupled to the input stage, for generating an output signal according to an output of the input stage; a first current source, for providing a first bias current; a second current source, for providing a second bias current identical to the first bias current; an Ahuja compensation circuit, comprising: a matched transistor pair, coupled to the first current source and the second current source; a capacitor coupled between the matched transistor pair and the output stage; and a transconductance boosting circuit, coupled to the matched transistor pair, for boosting transconductance of the matched transistor pair.

Abstract: A driving amplifier circuit includes: a first driver for souring a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) coupled to a differential input signal for driving the first driver; a second operational amplifier coupled to the differential input signal for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit, coupled to the first bias circuit and the second bias circuit, for enabling either the first bias circuit or the second bias circuit according to a control signal; and a digital control circuit, coupled to the enabling circuit, for monitoring currents of the first driver and the second driver to generate the control signal.

Abstract: A differential current amplifier circuit includes a first circuit generating a first pair of output currents based on a first input current to the differential current amplifier circuit. A second circuit generates a second pair of output currents based on a second input current to the differential current amplifier circuit. A first subtraction circuit generates a first output voltage based on a difference between one of the first pair of output currents and one of the second pair of output currents. A second subtraction circuit generates a second output voltage based on a difference between the other one of the second pair of output currents and the other one of the first pair of output currents.

Abstract: A pulse-width modulated buck regulator includes a feedback control without having any external frequency compensation components to stabilize the feedback control loop irrespective of the reactive component of its load impedance. Additionally, the output voltage is maintained constant not only with feedback but also using a power supply voltage compensation scheme. Thus, the feedback control compensates for resistive losses, thus minimizing hardware. The output voltage is compared with first and second reference voltages. If the output voltage is greater than the first reference voltage, a counter's count is decremented. If the output voltage is less than the second reference voltage, the counter's count is incremented. The counter is disabled if the output voltage is smaller than the first reference voltage and greater than the second reference voltage. The duty cycle of the output voltage is varied in accordance with the counter's count.

Abstract: An amplifier circuit includes a first stage that receives a signal input and a control input and that generates first stage outputs. A second stage that communicates with the first stage and the control input and that includes a current source drivers. Each of the current source drivers have a constant current source mode and a driver mode. The constant current source mode and the driver mode are selected based on the signal input and the control input. A comparator circuit compares current through the current source drivers with a reference current. A control circuit generates the control input based on the comparison.

Abstract: A differential current amplifier circuit comprises a first low input impedance circuit that generates a first output current based on a first input current to the differential current amplifier circuit. A second low input impedance circuit generates a second output current based on a second input current to the differential current amplifier circuit. A first current subtraction circuit generates a first output voltage based on a difference between the first and the second output currents. A second current subtraction circuit generates a second output voltage based on a difference between the second and the first output currents.

Abstract: A Gigabit/s transimpedance amplifier system includes a forward-path amplifier section with a very large bandwidth and an overall frequency-selective feedback section which is active only from DC to low frequencies. The forward-path of the amplifier comprises a regulated cascode for receiving the input signal, a regulated cascode for receiving the feedback signal, a single-ended to differential converter and an output buffer. Stability and frequency selection is achieved by a bandwidth-limited operational amplifier in the feedback path. The Miller multiplication of a capacitive means in the operational amplifier creates a low-frequency pole and stabilizes the feedback loop and thereby limits the frequency range of the feedback.

Abstract: Chopper amplifiers and methods of amplification are provided. A circuit includes an adjustable modulation resistance network, an amplifier, and an adjustable feedback resistance network. The adjustable modulation resistance network receives and modulates an input signal to produce a modulated signal including varying an input resistance, which includes a switch resistance. The amplifier has an input and an output. The adjustable feedback resistance network varies a feedback resistance, which includes a switch resistance. In addition, a suppression circuit is also included that can produce the feedback signal for preventing the direct current offset signal from substantially affecting the output signal.

Abstract: A fully differential current feedback amplifier suitable for using in a fully differential operational amplifier circuit is disclosed. Symmetrical low input impedance input circuits receive a differential input current and provide a set of four currents that correspond to the differential input currents. These current are input to a pair of subtraction circuits that output a first voltage signal responsive to the positive difference and a second voltage signal responsive to the negative difference. In some embodiments these signals may be further amplified. A common mode circuit is provided that averages the output voltage and feeds back current in response to the subtraction circuits. In this way the average common mode output DC voltage can be set to particular voltage levels.

Abstract: A Gigabit/s transimpedance amplifier system includes a forward-path amplifier section with a very large bandwidth and an overall frequency-selective feedback section which is active only from DC to low frequencies. The forward-path of the amplifier comprises a regulated cascode for receiving the input signal, a regulated cascode for receiving the feedback signal, a single-ended to differential converter and an output buffer. Stability and frequency selection is achieved by a bandwidth-limited operational amplifier in the feedback path. The Miller multiplication of a capacitive means in the operational amplifier creates a low-frequency pole and stabilizes the feedback loop and thereby limits the frequency range of the feedback.

Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Abstract: This circuit and method provides an analog-to-digital A/D converter with minimal power and minimal integrated circuit area. A circuit and a method for A/D conversion are provided which maintains performance, but which uses fewer comparators than the prior art. This is achieved by a semi-flash analog-to-digital, A/D, converter circuit with minimal comparator count. The design does not use any subtraction or multiplication operation. It utilizes fewer comparators than the prior art semi-flash A/D converters. The prior art designs use 30 comparators for an 8-bit semi-flash A/D converter while this invention uses 8 comparators. This circuit and method does not require any external Sample and Hold, S/H circuits. It is a hybrid between flash A/Ds and successive approximation A/Ds.

Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Abstract: A relaxation current controlled oscillator (CCO) is provided by forming an integrator out of a transconductance amplifier and a capacitor. The output of the integrator is fed to comparators which in turn feed a bistable circuit. The outputs of the bistable circuit control either the polarity of the input signals to the transconductance amplifier or the polarity of the input signals to the comparators. Switches, controlled by the bistable circuit, in turn control the polarity of the input signals. The feedback path created by the transconductance amplifier, comparators, flip-flops, and switches produces continuous oscillations. A DC current input adjusts the gm of the transconductance amplifier allowing the oscillation frequency of the CCO to be adjusted. Several embodiments of CCOs are described which are fully compatible with PLLs with automatic time-constant or bandwidth tuning of a gm-C filter.

Abstract: A temperature compensating biasing circuit is constructed by first determining a piecewise function substantially describing a required bias current with respect to temperature. Reference signals are created such that each reference signal describes an amount of contributing currents that, when summed together, generate a master biasing current. The biasing current generator is further constructed to create a thermal signal indicating an operating temperature. Each of the reference signals is compared to the thermal signal. The biasing current generator then identifies which of the contributing currents or portions of the contributing currents are being included to generate the master biasing current. The identified contributing currents and the portions of the contributing currents are then summed to form the master biasing current. The master biasing current may be mirrored to form bias currents that have the temperature compensation bias function.

Abstract: A high frequency CMOS differential amplifier which comprises: a variable gain amplifier which amplifies differential input; a temperature sensing circuit; a gain-slope correction circuit which produces an intermediate control voltage as a function of temperature, thereby compensating for a change in slope of the gain control characteristics with temperature of the variable gain amplifier; a gain compensation circuit which is used to correct temperature/process variations of MOS transistors in high frequency differential amplifiers; and a bias control circuit.

Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Abstract: A temperature compensating biasing circuit is constructed by first determining a piecewise function substantially describing a required bias current with respect to temperature. Reference signals are created such that each reference signal describes an amount of contributing currents that, when summed together, generate a master biasing current. The biasing current generator is further constructed to create a thermal signal indicating an operating temperature. Each of the reference signals is compared to the thermal signal. The biasing current generator then identifies which of the contributing currents or portions of the contributing currents are being included to generate the master biasing current. The identified contributing currents and the portions of the contributing currents are then summed to form the master biasing current. The master biasing current may be mirrored to form bias currents that have the temperature compensation bias function.