Patents by Inventor Uday Mitra
Uday Mitra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705366Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.Type: GrantFiled: June 11, 2021Date of Patent: July 18, 2023Assignee: Micromaterials LLCInventors: He Ren, Amrita B. Mullick, Regina Freed, Mehul Naik, Uday Mitra
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Publication number: 20230008695Abstract: Exemplary integrated cluster tools may include a factory interface including a first transfer robot. The tools may include a wet clean system coupled with the factory interface at a first side of the wet clean system. The tools may include a load lock chamber coupled with the wet clean system at a second side of the wet clean system opposite the first side of the wet clean system. The tools may include a first transfer chamber coupled with the load lock chamber. The first transfer chamber may include a second transfer robot. The tools may include a dry etch chamber coupled with the first transfer chamber. The tools may include a second transfer chamber coupled with the first transfer chamber. The second transfer chamber may include a third transfer robot. The tools may include a process chamber coupled with the second transfer chamber.Type: ApplicationFiled: July 7, 2022Publication date: January 12, 2023Applicant: Applied Materials, Inc.Inventors: Brian K. Kirkpatrick, Uday Mitra
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Publication number: 20220359289Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 11437274Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: GrantFiled: September 14, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 11232955Abstract: Processing methods to etch metal oxide films with less etch residue are described. The methods comprise etching a metal oxide film with a metal halide etchant, and exposing the etch residue to a reductant to remove the etch residue. Some embodiments relate to etching tungsten oxide films. Some embodiments utilize tungsten halides to etch metal oxide films. Some embodiments utilize hydrogen gas as a reductant to remove etch residues.Type: GrantFiled: March 26, 2020Date of Patent: January 25, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Amrita B. Mullick, Abhijit Basu Mallick, Srinivas Gandikota, Susmit Singha Roy, Yingli Rao, Regina Freed, Uday Mitra
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Publication number: 20220013624Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Applicant: Micromaterials LLCInventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu
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Patent number: 11164938Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.Type: GrantFiled: March 23, 2020Date of Patent: November 2, 2021Assignee: Micromaterials LLCInventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu
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Publication number: 20210305091Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Applicant: Micromaterials LLCInventors: He Ren, Amrita B. Mullick, Regina Freed, Mehul Naik, Uday Mitra
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Patent number: 11062942Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.Type: GrantFiled: December 10, 2018Date of Patent: July 13, 2021Assignee: Micromaterials LLCInventors: He Ren, Amrita B. Mullick, Regina Freed, Mehul Naik, Uday Mitra
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Patent number: 11037825Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to minimize bowing of the side walls during metal recess in a fully self-aligned via. The cap layer can be selectively removed, thus increasing the aspect ratio, by exposing the substrate to a hot phosphoric acid solution.Type: GrantFiled: August 25, 2020Date of Patent: June 15, 2021Assignee: Micromaterials LLCInventors: Amrita B. Mullick, Madhur Sachan, He Ren, Swaminathan Srinivasan, Regina Freed, Uday Mitra
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Publication number: 20210090952Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: ApplicationFiled: September 14, 2020Publication date: March 25, 2021Applicant: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 10892187Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a bridging via between a first metallization and a third metallization layer, the bridging via not contacting a second metallization layers. Methods of providing self-aligned bridging vias are also described.Type: GrantFiled: May 14, 2019Date of Patent: January 12, 2021Assignee: Micromaterials LLCInventors: Regina Freed, Uday Mitra, Sanjay Natarajan
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Patent number: 10892183Abstract: Methods to remove metal oxides from substrate surfaces are described. Some embodiments of the disclosure utilize an aqueous alkaline solution to remove metal oxides from substrate surfaces using a wet method. Some embodiments of the disclosure are performed at atmospheric pressure and lower temperatures. Methods of forming self-aligned vias are also described.Type: GrantFiled: March 1, 2019Date of Patent: January 12, 2021Assignee: Micromaterials LLCInventors: Amrita B. Mullick, Uday Mitra, Regina Freed
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Publication number: 20200388535Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to minimize bowing of the side walls during metal recess in a fully self-aligned via. The cap layer can be selectively removed, thus increasing the aspect ratio, by exposing the substrate to a hot phosphoric acid solution.Type: ApplicationFiled: August 25, 2020Publication date: December 10, 2020Applicant: Micromaterials LLCInventors: Amrita B. Mullick, Madhur Sachan, He Ren, Swaminathan Srinivasan, Regina Freed, Uday Mitra
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Publication number: 20200312953Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.Type: ApplicationFiled: March 23, 2020Publication date: October 1, 2020Applicant: Micromaterials LLCInventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu
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Patent number: 10790191Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to minimize bowing of the side walls during metal recess in a fully self-aligned via. The cap layer can be selectively removed, thus increasing the aspect ratio, by exposing the substrate to a hot phosphoric acid solution.Type: GrantFiled: May 6, 2019Date of Patent: September 29, 2020Assignee: MICROMATERIALS LLCInventors: Amrita B. Mullick, Madhur Sachan, He Ren, Swaminathan Srinivasan, Regina Freed, Uday Mitra
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Publication number: 20200227275Abstract: Processing methods to etch metal oxide films with less etch residue are described. The methods comprise etching a metal oxide film with a metal halide etchant, and exposing the etch residue to a reductant to remove the etch residue. Some embodiments relate to etching tungsten oxide films. Some embodiments utilize tungsten halides to etch metal oxide films. Some embodiments utilize hydrogen gas as a reductant to remove etch residues.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Applicant: Applied Materials, Inc.Inventors: Amrita B. Mullick, Abhijit Basu Mallick, Srinivas Gandikota, Susmit Singha Roy, Yingli Rao, Regina Freed, Uday Mitra
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Patent number: 10699953Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a liner that is selectively removable when compared to conductive lines. The liner may be selectively removed by utilizing one or more of a base (e.g. sodium hydroxide) and hydrogen peroxide.Type: GrantFiled: May 29, 2019Date of Patent: June 30, 2020Assignee: Micromaterials LLCInventors: Amrita B. Mullick, Nitin K. Ingle, Xikun Wang, Regina Freed, Uday Mitra, Ho-yung David Hwang
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Patent number: 10622221Abstract: Processing methods to etch metal oxide films with less etch residue are described. The methods comprise etching a metal oxide film with a metal halide etchant, and exposing the etch residue to a reductant to remove the etch residue. Some embodiments relate to etching tungsten oxide films. Some embodiments utilize tungsten halides to etch metal oxide films. Some embodiments utilize hydrogen gas as a reductant to remove etch residues.Type: GrantFiled: December 13, 2018Date of Patent: April 14, 2020Assignee: Applied Materials, Inc.Inventors: Amrita B. Mullick, Abhijit Basu Mallick, Srinivas Gandikota, Susmit Singha Roy, Yingli Rao, Regina Freed, Uday Mitra
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Publication number: 20200098633Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: ApplicationFiled: November 22, 2019Publication date: March 26, 2020Applicant: Micromaterials LLCInventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung David Hwang