Patents by Inventor Uday R. Savagaonkar

Uday R. Savagaonkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8819455
    Abstract: A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Uday R. Savagaonkar, David M. Durham, Niranjan L. Cooray, Men Long, Carlos V. Rozas, Alpa T. Narendra Trivedi
  • Patent number: 8799673
    Abstract: Systems, apparatuses, and methods, and for seamlessly protecting memory regions to protect against hardware-based attacks are disclosed. In one embodiment, an apparatus includes a decoder, control logic, and cryptographic logic. The decoder is to decode a transaction between a processor and memory-mapped input/output space. The control logic is to redirect the transaction from the memory-mapped input/output space to a system memory. The cryptographic logic is to operate on data for the transaction.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Uday R. Savagaonkar, Ravi Sahita, David Durham, Men Long
  • Publication number: 20140208109
    Abstract: A method and system to provide an effective, scalable and yet low-cost solution for Confidentiality, Integrity and Replay protection for sensitive information stored in a memory and prevent an attacker from observing and/or modifying the state of the system. In one embodiment of the invention, the system has strong hardware protection for its memory contents via XTS-tweak mode of encryption where the tweak is derived based on “Global and Local Counters”. This scheme offers to enable die-area efficient Replay protection for any sized memory by allowing multiple counter levels and facilitates using small counter-sizes to derive the “tweak” used in the XTS encryption without sacrificing cryptographic strength.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 24, 2014
    Inventors: Alpa T. Narendra Trivedi, David M. Durham, Men Long, Siddhartha Chhabra, Uday R. Savagaonkar, Carlos V. Rozas
  • Publication number: 20140196155
    Abstract: Methods, apparatuses and storage medium associated digital rights management (DRM) using DRM locker is disclosed herein. In embodiments, a DRM locker is provided to a client device. The DRM locker may be configured to store a number of DRM licenses or keys for a number of DRM protected contents. The DRM locker, on presentation of an associated locker key, may respond to a request for one or more of the stored DRM licenses or keys, to enable consumption of the corresponding DRM protected contents using the client device. Other embodiments may be disclosed or claimed.
    Type: Application
    Filed: March 11, 2014
    Publication date: July 10, 2014
    Inventors: Christopher J. McConnell, Uday R. Savagaonkar
  • Publication number: 20140189326
    Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Rebekah Leslie, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith
  • Publication number: 20140189242
    Abstract: Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Francis X. Mckeen, Michael A. Goldsmith, Barrey E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith
  • Publication number: 20140189274
    Abstract: An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Gur Hildesheim, Ittai Anati, Hisham Shafi, Shlomo Raikin, Gideon Gerzon, Uday R Savagaonkar, Carlos V Rozas, Francis X McKeen, Michael A Goldsmith, Dewan Prashant
  • Publication number: 20140189325
    Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Francis X. Mckeen, Michael A. Goldsmith, Barry E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Ittai Anati, Ilya Alexandrovich, Alex Berenzon
  • Publication number: 20140189246
    Abstract: Embodiments of an invention for measuring applications loaded in secure enclaves at runtime are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to extend a first measurement of a secure enclave with a second measurement. The execution unit is to execute the instruction after initialization of the secure enclave.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Inventors: Bin Xing, Matthew E. Hoekstra, Michael A. Goldsmith, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Francis X. Mckeen, Stephen J. Tolopka
  • Publication number: 20140156972
    Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Inventors: Vedyvas Shanbhogue, Jason W. Brandt, Uday R. Savagaonkar, Ravi L. Sahita
  • Publication number: 20140157410
    Abstract: In accordance with some embodiments, a protected execution environment may be defined for a graphics processing unit. This framework not only protects the workloads from malware running on the graphics processing unit but also protects those workloads from malware running on the central processing unit. In addition, the trust framework may facilitate proof of secure execution by measuring the code and data structures used to execute the workload. If a part of the trusted computing base of this framework or protected execution environment is compromised, that part can be patched remotely and the patching can be proven remotely throughout attestation in some embodiments.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Inventors: Prashant Dewan, Uday R. Savagaonkar, David M. Durham, Paul S. Schmitz, Jason Martin, Michael Goldsmith, Ravi L. Sahita, Frank X McKeen, Carlos Rozas, Vembu Balaji, Scott Janus, Geoffrey S. Strongin, Xiaozhu Kang, Karanvir S. Grewal, Siddhartha Chhabra, Alpha T. Narendra Trivedi
  • Publication number: 20140123235
    Abstract: Enabling access control caches for co-processors to be charged using a VMX-nonroot instruction. As a result a transition to VMX-root is not needed, saving the cycles involved in such a transition.
    Type: Application
    Filed: December 28, 2011
    Publication date: May 1, 2014
    Inventors: Prashant Dewan, Jason Martin, Uday R. Savagaonkar, Carlos V. Rozas
  • Patent number: 8707450
    Abstract: Methods, apparatuses and storage medium associated digital rights management (DRM) using DRM locker is disclosed herein. In embodiments, a DRM locker is provided to a client device. The DRM locker may be configured to store a number of DRM licenses or keys for a number of DRM protected contents. The DRM locker, on presentation of an associated locker key, may respond to a request for one or more of the stored DRM licenses or keys, to enable consumption of the corresponding DRM protected contents using the client device. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Christopher J. McConnell, Uday R. Savagaonkar
  • Publication number: 20140101461
    Abstract: A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Inventors: Siddhartha Chhabra, Uday R. Savagaonkar, David M. Durham, Niranjan L. Cooray, Men Long, Carlos V. Rozas, Alpa T. Narendra Trivedi
  • Publication number: 20140096068
    Abstract: A device and method for securely rendering content on a gesture-enabled computing device includes initializing a secure execution environment on a processor graphics of the computing device. The computing device transfers view rendering code and associated state data to the secure execution environment. An initial view of the content is rendered by executing the view rendering code in the secure execution environment. A gesture is recognized, and an updated view of the content is rendered in the secure execution environment in response to the gesture. The gesture may include a touch gesture recognized on a touch screen, or a physical gesture of the user recognized by a camera. After the updated view of the content is rendered, the main processor of the computing device may receive updated view data from the secure execution environment.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Prashant Dewan, Siddhartha Chhabra, Xiaozhu Kang, Xiaoning Li, Uday R. Savagaonkar, David M. Durham, Paul S. Schmitz, Michael A. Goldsmith, Jason Martin
  • Publication number: 20140089659
    Abstract: Keying materials used for providing security in a platform are securely provisioned both online and offline to devices in a remote platform. The secure provisioning of the keying materials is based on a revision of firmware installed in the platform.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 27, 2014
    Inventors: Ernest F. Brickell, Shay Gueron, Jiangtao Li, Carlos V. Rozas, Daniel Nemiroff, Vincent R. Scarlata, Uday R. Savagaonkar, Simon P. Johnson
  • Publication number: 20140041045
    Abstract: Methods, apparatuses and storage medium associated digital rights management (DRM) using DRM locker is disclosed herein. In embodiments, a DRM locker is provided to a client device. The DRM locker may be configured to store a number of DRM licenses or keys for a number of DRM protected contents. The DRM locker, on presentation of an associated locker key, may respond to a request for one or more of the stored DRM licenses or keys, to enable consumption of the corresponding DRM protected contents using the client device. Other embodiments may be disclosed or claimed.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Inventors: Christopher J. McConnell, Uday R. Savagaonkar
  • Publication number: 20140040632
    Abstract: A method and system to provide a low-overhead cryptographic scheme that affords memory confidentiality, integrity and replay-protection by removing the critical read-after-write dependency between the various levels of the cryptographic tree. In one embodiment of the invention, the cryptographic processing of a child node can be pipelined with that of the parent nodes. This parallelization provided by the invention results in an efficient utilization of the cryptographic pipeline, enabling significantly lower performance overheads.
    Type: Application
    Filed: December 28, 2011
    Publication date: February 6, 2014
    Inventors: Siddhartha Chhabra, Uday R. Savagaonkar, Carlos V. Rozas, Alpa T. Narendra Trivedi, Men Long, David M. Durham
  • Patent number: 8560806
    Abstract: Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, and determination logic. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 15, 2013
    Assignee: Intel Corporation
    Inventors: David M. Durham, Uday R. Savagaonkar, Ravi Sahita
  • Patent number: 8549254
    Abstract: Embodiments of an invention for using a translation lookaside buffer to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventor: Uday R. Savagaonkar