Abstract: Embodiments disclosed herein relate to reducing power consumption of an electronic device scanning for wireless communication signals while maintaining or even improving an efficiency of the scanning operations. To do so, the electronic device may include more than one scan core, such as a main core and a receiving core. The receiving core may have limited functionality compared to the main core. For example, the receiving core may only receive wireless signals (including scanning for wireless signals). That is, the receiving core may not support certain operations that consume relative high power that are supported by the main core, such as transmission of signals. In this way, operation of the receiving core, either in place of or in addition to the main core, may reduce power consumption of the electronic device by avoiding high power consuming operations, such as data transmission, while scanning for various signals.

Abstract: Circuits, methods, and apparatus that may estimate the power being consumed by an OLED display screen of an electronic device, may provide further information about that power usage, may modify or change functions performed by the electronic device based on that power usage, and may inform an application's developer about the amount of power being used by the electronic device while the electronic device is running the application. One example may estimate the power being used by an OLED display screen of an electronic device by determining the content of images being displayed during a duration. The estimated power may then be presented to a user. The estimated power may be used in decisions to modify or change parameters of the screen or other device components.

Abstract: Circuits, methods, and apparatus that may estimate the power being consumed by an OLED display screen of an electronic device, may provide further information about that power usage, may modify or change functions performed by the electronic device based on that power usage, and may inform an application's developer about the amount of power being used by the electronic device while the electronic device is running the application. One example may estimate the power being used by an OLED display screen of an electronic device by determining the content of images being displayed during a duration. The estimated power may then be presented to a user. The estimated power may be used in decisions to modify or change parameters of the screen or other device components.

Abstract: Circuits, methods, and apparatus that may estimate the power being consumed by an OLED display screen of an electronic device, may provide further information about that power usage, may modify or change functions performed by the electronic device based on that power usage, and may inform an application's developer about the amount of power being used by the electronic device while the electronic device is running the application. One example may estimate the power being used by an OLED display screen of an electronic device by determining the content of images being displayed during a duration. The estimated power may then be presented to a user. The estimated power may be used in decisions to modify or change parameters of the screen or other device components.

Abstract: Circuits, methods, and apparatus that may estimate the power being consumed by an OLED display screen of an electronic device, may provide further information about that power usage, may modify or change functions performed by the electronic device based on that power usage, and may inform an application's developer about the amount of power being used by the electronic device while the electronic device is running the application. One example may estimate the power being used by an OLED display screen of an electronic device by determining the content of images being displayed during a duration. The estimated power may then be presented to a user. The estimated power may be used in decisions to modify or change parameters of the screen or other device components.

Abstract: Apparatus and methods for configuring wireless circuitry of a wireless device to optimize power consumption based on operating states of the wireless device are disclosed. When associating with or while associated with a multiple-input multiple-output (MIMO) capable wireless local area network (WLAN) access point (AP), the wireless device configures the wireless circuitry to use a MIMO mode that includes at least two spatial streams for communication with multiple radio frequency (RF) receive chains active, a single-input single-output (SISO) mode or a multiple-input single-output (MISO) mode that includes only one spatial stream and a single RF receive chain active, or a single-input multiple-output (SIMO) mode that includes only one spatial stream and multiple RF receive chains active, based on balancing application requirements for data throughput with power saving modes to conserve battery levels. MIMO modes can be used when an active application benefits from MIMO rates or when transferring large files.

Abstract: Apparatus and methods for configuring wireless circuitry of a wireless device to optimize power consumption based on operating states of the wireless device are disclosed. When associating with or while associated with a multiple-input multiple-output (MIMO) capable wireless local area network (WLAN) access point (AP), the wireless device configures the wireless circuitry to use a MIMO mode that includes at least two spatial streams for communication with multiple radio frequency (RF) receive chains active, a single-input single-output (SISO) mode or a multiple-input single-output (MISO) mode that includes only one spatial stream and a single RF receive chain active, or a single-input multiple-output (SIMO) mode that includes only one spatial stream and multiple RF receive chains active, based on balancing application requirements for data throughput with power saving modes to conserve battery levels. MIMO modes can be used when an active application benefits from MIMO rates or when transferring large files.

Abstract: An accelerator chip can be positioned between a processor chip and a memory: The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: A Java accelerator includes a hardware unit associated with the CPU portion, the hardware unit converting stack-based instructions, such as Java bytecodes, into register-based instructions such as the instructions which are native to the CPU. A thread lifetime unit in the hardware unit is used to maintain a count of the number of bytecodes to be executed while an active thread is loaded into the system. Once this count reaches zero or below, the operation of a/the thread in the system is stopped and the Java Virtual Machine loaded into the CPU portion in order to implement its thread manager. Additionally, a single step unit in the hardware unit allows the production of debugger indications after each stack-based instruction.

Abstract: A system for implementing Java methods is described in which a Java virtual machine replaces normal method invocation instructions with custom method invocation instructions which are recognized by a hardware translator. The hardware translator can then use stored instructions from a microcode unit to cause a processor to set up a special hardware unit.

Abstract: An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: A Java accelerator includes a hardware unit associated with the CPU portion, the hardware unit converting stack-based instructions, such as Java bytecodes, into register-based instructions such as the instructions which are native to the CPU. A thread lifetime unit in the hardware unit is used to maintain a count of the number of bytecodes to be executed while an active thread is loaded into the system. Once this count reaches zero or below, the operation of a/the thread in the system is stopped and the Java Virtual Machine loaded into the CPU portion in order to implement its thread manager. Additionally, a single step unit in the hardware unit allows the production of debugger indications after each stack-based instruction.