Abstract: A novel and useful linear, efficient, smart wideband CMOS hybrid power amplifier that combined an analog linear amplification path and a digital power amplification (DPA) path. PA path control logic analyzes the input I and Q signals and determines which amplification paths to steer the input I and Q signals to. The analog linear amplification path comprises digital to analog converters for both I and Q paths and one or more analog linear power amplifiers. The digital power amplification path comprises I and Q up-sampling circuits and I and Q RF DAC circuits (e.g., digital PA circuits). In operation, the PA path control logic compares the I and Q signals to thresholds (which may or may not be different) and based on the comparisons, selects one or more paths for the input I and Q signals. Whether the signals from the analog and digital amplification paths are to be combined or selected (i.e.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A device and method of predistortion linearization that account for both EVM and spectral mask are disclosed. The device and method are based on transforming the predistorter optimization problem from the time domain to the frequency domain, and weighting the equations according to one or more desired objectives. One objective focuses on abiding by the spectral mask, whereas another objective focuses on improving the EVM.

Abstract: A novel and useful linear, efficient, smart wideband CMOS hybrid power amplifier that combined an analog linear amplification path and a digital power amplification (DPA) path. PA path control logic analyzes the input I and Q signals and determines which amplification paths to steer the input I and Q signals to. The analog linear amplification path comprises digital to analog converters for both I and Q paths and one or more analog linear power amplifiers. The digital power amplification path comprises I and Q up-sampling circuits and I and Q RF DAC circuits (e.g., digital PA circuits). In operation, the PA path control logic compares the I and Q signals to thresholds (which may or may not be different) and based on the comparisons, selects one or more paths for the input I and Q signals. Whether the signals from the analog and digital amplification paths are to be combined or selected (i.e.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: The subject matter discloses an apparatus residing within an RF chip, comprising: a detection unit for detecting IQ mismatch in an IQ signal; an analog calibration module comprising a first analog calibration mechanism for calibrating IQ mismatch in the phase component and a second analog calibration mechanism for calibrating IQ mismatch in the amplitude component; and a control unit for determining a calibration sequence of the IQ signal.

Abstract: A device and method of fast automatic gain control in quadrature receivers are disclosed. The AGC activity between the I and Q branches is split where in one branch the receive chain is in a certain gain state and in the other branch the receive chain is in another possible gain state, resulting in a significant shortening of the AGC duration of any IQ receiver.

Abstract: A device and method of predistortion linearization that account for both EVM and spectral mask are disclosed. The device and method are based on transforming the predistorter optimization problem from the time domain to the frequency domain, and weighting the equations according to one or more desired objectives. One objective focuses on abiding by the spectral mask, whereas another objective focuses on improving the EVM.

Abstract: The subject matter discloses an apparatus residing within an RF chip, comprising: a detection unit for detecting IQ mismatch in an IQ signal; an analog calibration module comprising a first analog calibration mechanism for calibrating IQ mismatch in the phase component and a second analog calibration mechanism for calibrating IQ mismatch in the amplitude component; and a control unit for determining a calibration sequence of the IQ signal.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A device and method of fast automatic gain control in quadrature receivers are disclosed. The AGC activity between the I and Q branches is split where in one branch the receive chain is in a certain gain state and in the other branch the receive chain is in another possible gain state, resulting in a significant shortening of the AGC duration of any IQ receiver.

Abstract: A digital nonlinear adaptive mechanism for frequency offset compensation for use in a digital Frequency Shift Keying (FSK) receiver such as a Bluetooth GFSK receiver. The mechanism is intended to aid in the recovery of a frequency-modulated signal in the presence of an unknown additive frequency offset, which could be greater than the peak frequency deviation and which must be suppressed to enable proper data recovery in the receiver. The mechanism utilizes a demodulator to convert the frequency offset into a digitally represented DC level. This level is extracted by a non-linear estimator based on peak detectors and filters. Active suppression of the DC level is achieved by feed-forwarding the estimated value into a subtractor that removes it from the digital signal. A gear shift mechanism incorporated within the DC estimation block enables the dynamic control of the DC estimation process.

Abstract: A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL. The oversampling timing mechanism generates appropriate timing instances, typically for the purpose of sampling a received data signal in a digital communications system, without requiring a specific external clock source but rather by utilizing a clock source having any arbitrary frequency. The mechanism of the present invention is especially suited for use in applications where a specific external clock source (e.g., integer multiple of the data rate) is not available and wherein the implications of the use of a PLL cannot be tolerated. The oversampling clock estimation mechanism generates a clock signal which may be unevenly distributed over the symbol period, but whereby on average, the correct number of samples is produced over a specific time duration.

Abstract: A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after downconversion to zero-IF and image rejection are performed. The phase of the input I and Q signals is determined using the principle that the phase is equivalent to arctan ( Q I ) . A lookup table stores the values of the arctan function preferably in a reduced size format. The size of the lookup table can be reduced significantly by storing arctan values for the first quadrant only (i.e. 0 to 90°) and taking advantage of the fact that the phase values for the other three quadrants can be derived from those of the first with some correction applied depending on the signs of the I and Q input samples. Phase extraction logic is provided that is operative to map the phase into the entire 0 to 360° range of phase values (i.e. ?? to +? radians) based on the signs of the I and Q signals.

Abstract: A digital nonlinear adaptive mechanism for frequency offset compensation for use in a digital Frequency Shift Keying (FSK) receiver such as a Bluetooth GFSK receiver. The mechanism is intended to aid in the recovery of a frequency-modulated signal in the presence of an unknown additive frequency offset, which could be greater than the peak frequency deviation and which must be suppressed to enable proper data recovery in the receiver. The mechanism utilizes a demodulator to convert the frequency offset into a digitally represented DC level. This level is extracted by a non-linear estimator based on peak detectors and filters. Active suppression of the DC level is achieved by feed-forwarding the estimated value into a subtractor that removes it from the digital signal. A gear shift mechanism incorporated within the DC estimation block enables the dynamic control of the DC estimation process.

Abstract: A nonlinear adaptive mechanism for amplitude adjustment and DC estimation and compensation for use in a digital receiver such as a Bluetooth GFSK receiver. The mechanism uses a feed-forward technique that can be used in a multi-stage scheme to perform both DC compensation and amplitude adjustment of an input signal for use by subsequent processing stages. In a first stage, coarse DC offset compensation is performed and the offset estimates generated are subsequently frozen. In a second stage, the incoming signal with the DC offset subtracted from it, is then scaled into a narrow predefined range of amplitudes using a scaling mechanism that works with gains and attenuations that are powers of two in order to simplify implementation. In a third stage, the scaled compensated signal is then injected again into the same DC estimation mechanism, which was previously used for DC compensation in the first stage, for further DC offset estimation and compensation (i.e. fine DC estimation and compensation).

Abstract: A nonlinear adaptive mechanism for amplitude adjustment and DC estimation and compensation for use in a digital receiver such as a Bluetooth GFSK receiver. The mechanism uses a feed-forward technique that can be used in a multi-stage scheme to perform both DC compensation and amplitude adjustment of an input signal for use by subsequent processing stages. In a first stage, coarse DC offset compensation is performed and the offset estimates generated are subsequently frozen. In a second stage, the incoming signal with the DC offset subtracted from it, is then scaled into a narrow predefined range of amplitudes using a scaling mechanism that works with gains and attenuations that are powers of two in order to simplify implementation. In a third stage, the scaled compensated signal is then injected again into the same DC estimation mechanism, which was previously used for DC compensation in the first stage, for further DC offset estimation and compensation (i.e. fine DC estimation and compensation).

Abstract: A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after downconversion to zero-IF and image rejection are performed. The phase of the input I and Q signals is determined using the principle that the phase is equivalent to arctan 1 ( Q I ) .