Patents by Inventor Udo Krautz
Udo Krautz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10303438Abstract: A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.Type: GrantFiled: January 16, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tina Babinsky, Udo Krautz, Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner
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Publication number: 20180203667Abstract: A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.Type: ApplicationFiled: January 16, 2017Publication date: July 19, 2018Inventors: Tina BABINSKY, Udo KRAUTZ, Klaus M. KROENER, Silvia M. MUELLER, Andreas WAGNER
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Patent number: 9703907Abstract: A computer-implemented method includes identifying an electronic circuit, which includes a plurality of circuit elements and is based on a circuit design. The circuit design includes structural information and logical information. The method generates a first verification model for the circuit design. The verification model includes a plurality of error report signal paths for each of the plurality of circuit elements. The method identifies a first circuit element output based on the plurality of error report signal paths. The method sets output for at least one of the first plurality of circuit elements to a fixed value. The method generates a second circuit element output based on the plurality of error report signal paths and setting output for at least one of the first plurality of circuit elements to a fixed value. The method determines a difference between the first circuit element output and the second circuit element output.Type: GrantFiled: October 27, 2015Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Christian Jacobi, Udo Krautz
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Publication number: 20170116362Abstract: A computer-implemented method includes identifying an electronic circuit, which includes a plurality of circuit elements and is based on a circuit design. The circuit design includes structural information and logical information. The method generates a first verification model for the circuit design. The verification model includes a plurality of error report signal paths for each of the plurality of circuit elements. The method identifies a first circuit element output based on the plurality of error report signal paths. The method sets output for at least one of the first plurality of circuit elements to a fixed value. The method generates a second circuit element output based on the plurality of error report signal paths and setting output for at least one of the first plurality of circuit elements to a fixed value. The method determines a difference between the first circuit element output and the second circuit element output.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: Christian Jacobi, Udo Krautz
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Patent number: 9600616Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.Type: GrantFiled: September 13, 2016Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eli Arbel, Erez Barak, Bodo Hoppe, Udo Krautz, Shiri Moran
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Patent number: 9569573Abstract: A computer-implemented method includes identifying an electronic circuit, which includes a plurality of circuit elements and is based on a circuit design. The circuit design includes structural information and logical information. The method generates a first verification model for the circuit design. The verification model includes a plurality of error report signal paths for each of the plurality of circuit elements. The method identifies a first circuit element output based on the plurality of error report signal paths. The method sets output for at least one of the first plurality of circuit elements to a fixed value. The method generates a second circuit element output based on the plurality of error report signal paths and setting output for at least one of the first plurality of circuit elements to a fixed value. The method determines a difference between the first circuit element output and the second circuit element output.Type: GrantFiled: March 7, 2016Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Christian Jacobi, Udo Krautz
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Patent number: 9483591Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.Type: GrantFiled: November 27, 2015Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eli Arbel, Erez Barak, Bodo Hoppe, Udo Krautz, Shiri Moran
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Patent number: 9471327Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.Type: GrantFiled: August 20, 2013Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
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Patent number: 9459878Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.Type: GrantFiled: January 9, 2014Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
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Patent number: 9274791Abstract: A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.Type: GrantFiled: December 17, 2013Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Udo Krautz, Ulrike Schmidt
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Patent number: 9268563Abstract: A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.Type: GrantFiled: November 12, 2012Date of Patent: February 23, 2016Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Udo Krautz, Ulrike Schmidt
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Publication number: 20150058604Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.Type: ApplicationFiled: January 9, 2014Publication date: February 26, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anand B. Arunagiri, UDO KRAUTZ, SUJEET KUMAR, VIRESH PARUTHI
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Publication number: 20150058601Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.Type: ApplicationFiled: August 20, 2013Publication date: February 26, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
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Patent number: 8918747Abstract: A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a design under test using at least a first and a second instance of the logic design; initializing the instruction pipeline using the first instance of the design under test with the same value in each instruction pipeline stage and the second instance with random values in its pipeline stages; selecting an instruction of the processor execution unit out of a plurality of instructions and simultaneously issuing the instruction to each instance of the design under test; providing a comparison between the outputs of the instruction pipeline executing the instruction for each instance; and if the instruction is verifiable by formal model checking, approving the correctness of the logic design if the comparison result is true.Type: GrantFiled: November 6, 2013Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Maarten Jokob Boersma, Udo Krautz, Ulrike Schmidt
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Publication number: 20140195785Abstract: A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a design under test using at least a first and a second instance of the logic design; initializing the instruction pipeline using the first instance of the design under test with the same value in each instruction pipeline stage and the second instance with random values in its pipeline stages; selecting an instruction of the processor execution unit out of a plurality of instructions and simultaneously issuing the instruction to each instance of the design under test; providing a comparison between the outputs of the instruction pipeline executing the instruction for each instance; and if the instruction is verifiable by formal model checking, approving the correctness of the logic design if the comparison result is true.Type: ApplicationFiled: November 6, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten Jakob BOERSMA, Udo KRAUTZ, Ulrike SCHMIDT
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Publication number: 20140156969Abstract: A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.Type: ApplicationFiled: December 17, 2013Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MAARTEN J. BOERSMA, UDO KRAUTZ, ULRIKE SCHMIDT
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Publication number: 20140136815Abstract: A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.Type: ApplicationFiled: November 12, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten J. Boersma, Udo Krautz, Ulrike Schmidt
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Publication number: 20120330637Abstract: A method is provided for providing a debugging tool for a hardware design specified in a hardware description language. The method includes receiving one or multiple source files of the specified hardware design; processing each source file in a way that hardware description language constructs from the hardware design are directly simulatable; wherein the processing process includes at least one of the following: restructuring procedural source code of the source file; preserving functional equivalence to unaltered source code of the source file; and adding debug information to the hardware description of said source file.Type: ApplicationFiled: June 15, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Udo KRAUTZ, Stefan LETZ
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Patent number: 7949968Abstract: An improved method, system and computer-readable medium for constructing binary decision diagrams for a netlist graph is disclosed. The method comprises traversing a netlist graph in a depth-first manner. At least one binary decision diagram is built for one input of a node of the netlist graph using a binary decision diagram for the other input of that node as a don't-care condition.Type: GrantFiled: March 8, 2007Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Christian Jacobi, Udo Krautz, Viresh Paruthi, Matthias Pflanz, Kai O. Weber
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Patent number: 7890903Abstract: A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.Type: GrantFiled: May 29, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Kai Weber, Matthias Pflanz, Christian Jacobi, Udo Krautz