Abstract: A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.

Abstract: A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.

Abstract: A communication system for an HDMI communication interface CEC channel includes a communication module for receiving messages via the CEC channel, a processing unit for processing the received messages and an oscillator for driving the communication module. When the interface is in an active mode, the system is operative to activate the timer upon detection of the start of transmission of a first message, detect the initial bit of the first message, reconstruct and process the first message, and switch the interface from the active mode to standby by deactivating the oscillator. When the interface is in standby, the system is operative to switch the interface to the active condition by activating the oscillator and the timer when the start of a transmission of a second message is detected, detect the initial bit of a transmission of the second message, and reconstruct and process the second message.

Abstract: A communication system for an HDMI communication interface CEC channel includes a communication module for receiving messages via the CEC channel, a processing unit for processing the received messages and an oscillator for driving the communication module. When the interface is in an active mode, the system is operative to activate the timer upon detection of the start of transmission of a first message, detect the initial bit of the first message, reconstruct and process the first message, and switch the interface from the active mode to standby by deactivating the oscillator. When the interface is in standby, the system is operative to switch the interface to the active condition by activating the oscillator and the timer when the start of a transmission of a second message is detected, detect the initial bit of a transmission of the second message, and reconstruct and process the second message.

Abstract: An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.

Abstract: A circuit switches between at least a first clock signal and a second clock signal belonging to a plurality of clock signals available in an electronic device in response to the corresponding switch command, which comprises a selection module to select at a switch instant said second clock signal in said plurality of clock signals under the control of a signal selector and provide a selected clock signal.