Abstract: The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photosensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.

Abstract: Etching solutions are disclosed for etching low-k dielectric layers on substrates, said solutions including effective proportions of an oxidant for oxidizing a low-k dielectric layer and effective proportions of an oxide etchant for removing oxides. It is possible to easily remove a low-k dielectric layer using such etching solutions by a single-stage treatment process.

Abstract: The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photsensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.

Abstract: A method for fabricating a semiconductor device, for example a non-volatile memory device having a stacked gate (memory cell) consisting of a floating gate, a control gate deposited over the floating gate, and a dielectric interlayer interposed between them, comprises the steps of sequentially depositing: a tunnel oxide layer, a first polysilicon layer for the floating gate, and a nitride layer over a semiconductor substrate, sequentially etching the nitride layer, first polysilicon layer, and semiconductor substrate to form a trench, depositing an oxide layer over the substrate to fill the trench, removing the oxide layer to the level of the nitride layer to attain a field region of the trench isolation, removing the nitride layer, subjecting the field region to a wet-chemical treatment, and depositing a second polysilicon layer for the floating gate over the substrate.