Abstract: A method and system for performing duty-cycle correction (DCC) on a clock signal is provided. The method provides a two-step duty cycle correction. The method can include performing a main DCC of a single-ended clock signal, to generate a duty cycle adjusted single-ended clock signal, wherein a duty cycle of the single-ended clock signal is corrected according to a received duty-cycle continuous control signal and converting the duty cycle adjusted single-ended clock signal to differential clock signals. The method can further include performing a trim DCC by correcting a duty cycle of the differential clock signals according to a duty-cycle trim control signal received and generated in dependence upon duty cycles detected from differential output clock signals to provide error-corrected differential clock signals.