Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

Abstract: A method performed by a memory chip is described. The method includes specially requesting additional refreshes for weak storage cells of the memory chip that deplete their charge more rapidly than other storage cells of the memory chip. The additional refreshes are added to a distributed baseline refresh command sequence that is applied to the weak storage cells and the other storage cells. The distributed baseline refresh command sequence has a refresh rate that is determined from charge depletion characteristics of the other storage cells.

Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.

Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.

Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

Abstract: Examples include techniques to change a mode of operation for a memory device. Examples include using information stored at a memory array of the memory device to program mode registers at the memory device to change the mode of operation to a first mode of operation that corresponds to a frequency set point associated with dynamic voltage and frequency scaling for a processor coupled with the memory device.

Abstract: An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively.

Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.

Abstract: A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.

Abstract: A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.

Abstract: In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package. The multiple memory dies are coupled in a daisy chain, and can be a vertical stack or in a planar formation. The memory chip or chips at the end of the chain store parity data, and the other devices store data. The multichip memory includes XOR (exclusive OR) logic to compute parity to store in the redundant parity chips.

Abstract: A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

Abstract: Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

Abstract: An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

Abstract: Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

Abstract: Exemplary embodiments provide a tiered error correction code (ECC) Chipkill system, comprising: a device ECC incorporated into at least a portion of a plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and a system-level ECC device external to the plurality of memory devices is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.

Abstract: Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

Abstract: A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.