Abstract: A control unit for DC-to-AC inverter having an addressing memory which is loaded with an addressing table by a microprocessor for a respective frequency range of the inverter output voltage. In the addressing table, a predetermined portion of information is provided for each addressing combination of the switches of the DC-to-AC inverter, the portion of information containing the addressing combination itself and the number of clock pulses for which the addressing combination will be present. The portions of information are interrogated at different speeds depending upon the desired inverter output frequency. A frequency divider is addressed by a clock generator, the frequency divider receiving a division factor from the memory, the division factor being inversely proportional to the desired DC-to-AC inverter output frequency. The output signal of the divider decrements a counter which is loaded with a number of clock pulses associated with the respective addressing combination.

Abstract: An evaluation circuit for receiving the output signals from a tachometer, the output signal consisting of first and second speed-proportional pulse trains which are phase-shifted with respect to one another in response to the direction of rotation. The evaluation circuit converts the phase-shifted pulse trains into a speed-proportional pulse train having a frequency which is four times that of the first and second pulse trains, and into a separate sign signal indicative of the direction of rotation. The first and second pulse trains are conducted to respective first and second signal memories which are controlled by a clock signal. In one embodiment, four possible states for the combined first and second pulse trains are assigned respective designating numbers. The count in a bidirectional counter is caused to follow changes in the designating numbers, the bidirectional counter counting pulses from the clock signal until such coincidence is achieved.