Patents by Inventor Ulises Morales
Ulises Morales has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230337909Abstract: A device for retinal neuromodulation therapy and extrafoveal (eccentric) reading in subjects affected by visual impairment with loss of central vision, comprising a first apparatus designed to assess the eccentric reading capabilities correlated to the retinal anatomy of the patient; the first apparatus comprises a still camera or video camera device adapted to visualize the retina while the patient performs preset visual tasks; the device further comprises a second apparatus which comprises a screen associated with a tracking device for tracking the eyes which is adapted to monitor the eye movements of the patient, the second apparatus being adapted to control the images transmitted by the screen in order to execute eccentric exercises for visual rehabilitation.Type: ApplicationFiled: January 12, 2021Publication date: October 26, 2023Inventors: Tommaso OCCHIPINTI, Marco Ulises MORALES ARROYO
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Patent number: 10742327Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: October 11, 2019Date of Patent: August 11, 2020Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Publication number: 20200044744Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Paul VOOIS, Ramiro Rogelio LOPEZ, Jorge Manuel FINOCHIETTO, Norman L. SWENSON, Mario Rafael HUEDA, Hugo Santiago CARRER, Vadim GUTNIK, Adrián Ulises MORALES, Martin Ignacio DEL BARCO, Martin Carlos ASINARI, Federico Nicolas PAREDES, Alfredo Javier TADDEI, Mauro Marcelo BRUNI, Damian Alfonso MORERO, Facundo Abel Alcides RAMOS, María Laura FERSTER, Elvio Adrian SERRANO, Pablo Gustavo QUIROGA, Roman Antonio ARENAS, Matias German SCHNIDRIG, Alejandro Javier SCHWOYKOSKI
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Patent number: 10491304Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: November 29, 2018Date of Patent: November 26, 2019Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, Maria Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Publication number: 20190109646Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: ApplicationFiled: November 29, 2018Publication date: April 11, 2019Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Paul VOOIS, Ramiro Rogelio LOPEZ, Jorge Manuel FINOCHIETTO, Norman L. SWENSON, Mario Rafael HUEDA, Hugo Santiago CARRER, Vadim GUTNIK, Adrián Ulises MORALES, Martin Ignacio DEL BARCO, Martin Carlos ASINARI, Federico Nicolas PAREDES, Alfredo Javier TADDEI, Mauro Marcelo BRUNI, Damian Alfonso MORERO, Facundo Abel Alcides RAMOS, María Laura FERSTER, Elvio Adrian SERRANO, Pablo Gustavo QUIROGA, Roman Antonio ARENAS, Matias German SCHNIDRIG, Alejandro Javier SCHWOYKOSKI
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Patent number: 10177851Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: July 12, 2017Date of Patent: January 8, 2019Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Publication number: 20180064157Abstract: The present invention discloses the use of subcritical or supercritical carbon dioxide for injecting additives to seeds, beans, nuts, cereals and pseudo-cereals.Type: ApplicationFiled: April 12, 2016Publication date: March 8, 2018Inventors: Ian Whitehead, Ulises Morales-Duran, Emily Hoi Ki Sin
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Publication number: 20170317759Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: ApplicationFiled: July 12, 2017Publication date: November 2, 2017Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Paul VOOIS, Ramiro Rogelio LOPEZ, Jorge Manuel FINOCHIETTO, Norman L. SWENSON, Mario Rafael HUEDA, Hugo Santiago CARRER, Vadim GUTNIK, Adrián Ulises MORALES, Martin Ignacio DEL BARCO, Martin Carlos ASINARI, Federico Nicolas PAREDES, Alfredo Javier TADDEI, Mauro Marcelo BRUNI, Damian Alfonso MORERO, Facundo Abel Alcides RAMOS, María Laura FERSTER, Elvio Adrian SERRANO, Pablo Gustavo QUIROGA, Roman Antonio ARENAS, Matias German SCHNIDRIG, Alejandro Javier SCHWOYKOSKI
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Patent number: 9735881Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: May 6, 2016Date of Patent: August 15, 2017Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro M. Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Patent number: 9337934Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: November 29, 2013Date of Patent: May 10, 2016Assignee: ClariPhy Communications, Inc.Inventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Ulises Morales, Martin Ignacio del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro M. Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, Laura Maria Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski