Abstract: One implementation is a method for fabricating a semiconductor on a substrate. A first layer is formed on the substrate. An implanted pattern is introduced into the first layer by implanting using a structured implantation mask arranged over the first layer. A structured second layer is formed on the first layer after removing the implantation mask. A first pattern is generated in the substrate using the second layer as a mask. The first layer is developed with regard to the implanted pattern. A second pattern is generated in the substrate using the first layer as a mask.

Abstract: A method of manufacturing a memory cell includes: forming a first electrode, depositing a first insulator material over the first electrode, forming a via in the first insulator material, depositing a resistivity changing material in the via without completely filling the via, and forming a second electrode contacting the resistivity changing material.

Abstract: A resist layer is deposited a resist layer on a first layer of a layered stack. The stack also includes a second layer below the first layer. The resist layer is processed with a lithographic method to achieve a first structured resist layer. At least a part of the first structured resist layer is trimmed to achieve a second structured resist layer having at least in parts a structure with a critical dimension smaller than obtainable by processing the resist with a lithographic method. The first layer is selectively removed from the second layer in the areas not covered by the second structured resist layer. The second layer is modified by implantation to become a layer with defined selectivity to the non-modified material. The remains of the first layer are removed. The non-modified structures of the second layer are removed to create a hardmask layer by the remaining layer. The layered stack is further structured with the hardmask layer.

Abstract: A resist layer is deposited a resist layer on a first layer of a layered stack. The stack also includes a second layer below the first layer. The resist layer is processed with a lithographic method to achieve a first structured resist layer. At least a part of the first structured resist layer is trimmed to achieve a second structured resist layer having at least in parts a structure with a critical dimension smaller than obtainable by processing the resist with a lithographic method. The first layer is selectively removed from the second layer in the areas not covered by the second structured resist layer. The second layer is modified by implantation to become a layer with defined selectivity to the non-modified material. The remains of the first layer are removed. The non-modified structures of the second layer are removed to create a hardmask layer by the remaining layer. The layered stack is further structured with the hardmask layer.

Abstract: A process for introducing structures that have different dimensions, particularly with regard to depth, in which just one lithography level is required, is disclosed. This is achieved by use of a layer stack deposited on a substrate, where one layer in particular is used to store information related to the dimensioning of the different structures. The layer is partially opened up to expose the substrate at locations corresponding to where deep structures are to be formed. Deep structures are subsequently etched into the substrate, after which the layer is opened up at locations corresponding to where shallow structures are to be formed. The latter locations are subsequently etched to the desired depth of the shallower structures. The process can be used instead of conventional the dual damascene technology for the structuring of contact holes and interconnects.

Abstract: The present invention relates to a process for etching a metal layer system. The metal layer system includes a first aluminum-containing layer, a second aluminum-containing layer, and an interlayer arranged between the two aluminum-containing layers. The interlayer consists of a material that is suitable for end-point detection. The etching process includes a first etching step, in which the upper aluminum-containing layer is etched using a first etching angle, and a second etching step, in which the lower aluminum-containing layer is etched using a second etching angle. The process switches between the first etching step and the second etching step as soon as the end-point detection has detected that the interlayer has been reached. Accordingly, the interlayer is arranged at a location at which it is intended for the process to switch from the first etching step to the second etching step.

Abstract: A process for introducing structures that have different dimensions, particularly with regard to depth, in which just one lithography level is required, is disclosed. This is achieved by use of a layer stack deposited on a substrate, where one layer in particular is used to store information related to the dimensioning of the different structures. The layer is partially opened up to expose the substrate at locations corresponding to where deep structures are to be formed. Deep structures are subsequently etched into the substrate, after which the layer is opened up at locations corresponding to where shallow structures are to be formed. The latter locations are subsequently etched to the desired depth of the shallower structures. The process can be used instead of conventional the dual damascene technology for the structuring of contact holes and interconnects.

Abstract: A light source and an array of detectors are provided for measuring the intensity light scattered by polymer film material deposited on the wall surface of a plasma chamber in an plasma etch reactor. When disadvantageous flaking starts, the intensity of scattered light increases, which can be monitored and answered by issuing a warning signal. Directly reflected light is measured by a second array of detectors arranged along a line on an inner surface wall that intersects with the reflected beam of light. Thus local distributions of contaminating particles can be examined. A suitable cleaning step is initiated, thus leading to a reduction of contaminating particles or metal impurities in semiconductor device manufacturing. Problems can be recognized during the etch process and time is additionally saved by the present in-situ measurement.

Abstract: An improved insitu hard mask open strategy is performed before carrying out a metal etching process. The method for opening the hard mask made of SiO2, Si3N4 or SiON includes providing a substrate having thereon at least one metal layer, the hard mask layer, and a patterned photoresist layer overlying the hard mask layer. The hard mask layer is etched in a plasma etching process using an etchant source gas which is formed of a fluorine containing gas and oxygen. The plasma processing chamber used for etching the hard mask layer is the same as the plasma processing chamber in which the at least one metal layer is etched in another plasma etching process after the hard mask layer has been etched.

Abstract: An improved insitu hard mask open strategy is performed before carrying out a metal etching process. The method for opening the hard mask made of SiO2, Si3N4 or SiON includes providing a substrate having thereon at least one metal layer, the hard mask layer, and a patterned photoresist layer overlying the hard mask layer. The hard mask layer is etched in a plasma etching process using an etchant source gas which is formed of a fluorine containing gas and oxygen. The plasma processing chamber used for etching the hard mask layer is the same as the plasma processing chamber in which the at least one metal layer is etched in another plasma etching process after the hard mask layer has been etched.

Abstract: The present invention relates to a process for etching a metal layer system. The metal layer system includes a first aluminum-containing layer, a second aluminum-containing layer, and an interlayer arranged between the two aluminum-containing layers. The interlayer consists of a material that is suitable for end-point detection. The etching process includes a first etching step, in which the upper aluminum-containing layer is etched using a first etching angle, and a second etching step, in which the lower aluminum-containing layer is etched using a second etching angle. The process switches between the first etching step and the second etching step as soon as the end-point detection has detected that the interlayer has been reached. Accordingly, the interlayer is arranged at a location at which it is intended for the process to switch from the first etching step to the second etching step.