Abstract: Circuitry for the summation, especially for generation, of scalar products, to which one summand in floating-point representation is conveyed per machine cycle (ZT), in which, after conversion into fixed point representation, it is received in a summing unit with an accumulator (AS1,-AS4) comprising the whole exponent range. The accumulator is subdivided into row sections, which are longer than the mantissa of the summands. Partial exponents (EPK1,-EPK4) generated in an exponent analyzer (EXA) control the mantissa positioner (PM) or are allocated to the mantissas and delivered continuously and cycle-wise to transfer registers (RE1,-RE4; RVS1,-RVS4; RNS1, RNS4), controlling summation row-wise. The carriers are allocated to the accumulator sections and intermediately stored in carry memory sections (CS1,-CS4) and are not added digit positionwise to the contents of each adjacent memory section until the sum is output, further carries being continuously processed.

Abstract: Circuitry for generating scalar products and sums of floating point numbers with maximum accuracy and circuitry and a method for electronic computers by which scalar products of floating point numbers of the type pi, qi, ES(b,l,e1,e2) are summed with full precision in a fixed point representation by means of a summing unit (ALU) and one or more accumulator registers (ARC1, ARC2) with cells (Ai, j) for storing of codes of a base b having a length (2l+ 2 e1+ 2e2) for fixed point representation and certain overflow positions. By control means (SHR, E, Contr) the mantissas of products are delivered depending on the value of the respective exponents into the summing unit (ALU). By control means (RD, Contro), rounding operations ( .circle. , , .gradient., .increment.) demanded by the higher level computer are performed, and a rounded floating point number (.quadrature. c .epsilon. S(b,l,e1,e2)) and overflow (OF) and underflow (UF) criteria are delivered.