Abstract: In the framework of the development of future, integrated wideband networks, specifically the arrangement of the switching networks and switching network controls is of particular importance.In a switching network arranged in accordance with a space-division multiplex switching network each switching point comprises a comparator, comparing the addresses of the trunk lines arranged column-by-column to the routing information. When there is multiple correspondence in a column a decision circuit assigned to the trunk line decides the order in which the switching points are to switch. In addition, an input buffer is connected to each supply line, in which buffer the blocks are temporatily stored until they can reach one of the trunk lines. To avoid the occurrence of bottle-necks in the performance of the switching network an input buffer is assigned to each switching point or the switching network is arranged column-by-column and built up of units of equal structure.

Abstract: In broadband space-division switching networks a multi-layer p.c. board is used for wiring the switching matrices of adjacent switching stages. In case of a plurality of links between the switching matrices a corresponding number of layers of the p.c. board can be provided. The connection of the individual layers of the p.c. board requires much expenditure in point of manufacturing engineering.This expenditure can be reduced in a surprisingly simple manner, when a canonical linkage in a p.c. board is introduced such, that link sections of the switching matrix are fanned out into groups onto a layer of the p.c. board and combined again. By dividing the links into sections, requirements as regards equal line length, reduction of space required and replacement in case of defects can be met in a simple manner.

Abstract: The invention relates to a switching network for a switching system in which cells are transmitted in accordance with a time division multiplex method and the through-connection is effected by means of the routing information contained in the header of the cells. The blocks arriving at the switching node are temporarily stored in a queuing buffer until a free frame is available. A switching network should be configured in such a manner that the number of buffer spaces can become as small as possible and buffer spaces only need to be provided for data which are to be forwarded via the associated serving trunk. To this end, it is proposed to allocate a comparator to each offering trunk, the comparator comparing the address of the serving trunk with the routing information and the cells supplied in the offering trunk only being entered into the buffer store associated with the serving trunk in the case of a correspondence between routing information and stored address of this serving trunk.

Abstract: In a switching system, more specifically a packet switching system, the flow control of the packets can be established by way of a datagram or by implementing the method of the virtual connection. For the optimization of the flow control the selected structure of the switching network is especially important.If the switching network is designed along the lines of a space-division multiplex switching network, each junction point of the bus bar system consisting of feeder lines and trunk lines has a comparator assigned thereto, which compares the addresses of the trunk lines arranged in columns with the routing information contained in the packet message headers. If, simultaneously, several of the auxiliary lines arranged in rows are to be connected through to one of the trunk lines arranged in a column, the order is determined by means of a decision circuit associated to each trunk line.

Abstract: Large-scale time-division switching arrangements often consist of a central switching network and a series of so-called concentrators. For establishing an H1 switching a series of wideband concentrators are connected to a central wideband switching network if the wideband concentrators are of a modular structure and communicate through an internal bus system and an interface circuit with the central wideband switching network connected thereto, a distribution switching in the direction of the subscriber station and a testing of the concentrators while in operation can be effected in a simple way.

Abstract: A buffer memory for an input line of a digital interface serves to adapt input data which exhibit large phase fluctuations with respect to the local clock of the interface to this local clock. To this end it is necessary to write the input data with the associated clock into the buffer, the data being read with the local clock. Depending on the phase shifts, write and read operation are then liable to occur simultaneously in border cases. In order to enable the use of conventional components in spite of the described phenomenon, the buffer memory is composed of a number of storage blocks which each comprise the same number of addresses, the storage blocks normally being cyclically addressed in succession. An address spacing monitoring device ensures that read and write operations are always performed only in different storage blocks, so that they can take place simultaneously.