Abstract: A method of forming an integrated circuit including a transistor is disclosed. One embodiment provides an active zone formed in a semiconductor substrate. Trench insulator structures and cell insulator structures are adjacent to the active zone. A gate electrode is formed including a buried portion. The buried portion is formed in a self-aligned manner with respect to the cell insulator structures.

Abstract: A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a transistor.

Abstract: A memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.

Abstract: A phase change memory device and method of forming a phase change memory device is disclosed. The method includes forming a memory device with a plurality of memory cells, each memory cell having a pillar containing a region of an active material, said method comprising the steps of: depositing at least a thermally insulating base layer on a surface that comprises said pillars; depositing a top layer on top of said base layer, said base layer having a higher resistance against polishing than said top layer; and planarizing a top surface by polishing such that at least the parts of said base layer above said pillars are exposed. The invention further relates to a memory device fabricated by this method.

Abstract: A memory includes transistors in rows and columns providing an array, first conductive lines in columns across the array, and second conductive lines encapsulated by dielectric material in rows across the array. Each second conductive line is coupled to one side of the source-drain path of the transistors in each row. The memory includes phase change elements between the second conductive lines and contacting the first conductive lines and self-aligned to the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of a transistor.

Abstract: A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.

Abstract: A transistor structure such as a FinFET is formed in a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches in the semiconductor substrate. First and second source/drain regions are arranged along the upper surface of the surface contour, with a recess structure between the first and second source/drain regions. The recess structure extends further into the semiconductor substrate than the first and second source/drain regions such that a channel within the semiconductor substrate between the first and second source/drain regions extends around the recess structure. The effective length of the channel is a function of the depth of the recess structure. A gate electrode is arranged along at least one of the sidewalls adjacent the channel. The effective channel width is a function of the depth to which the gate electrode is formed.

Abstract: Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

Abstract: A transistor, memory cell array and method of manufacturing a transistor are disclosed.

Abstract: The invention relates to the fabrication of DRAM memory cell arrangements having fin field effect transistors and curved channel field effect transistors. The FinFETs and CFETs are formed in a manner oriented to semiconductor fins arranged in cell rows. Within the cell rows, the semiconductor fins are spaced apart from one another by cell insulator structures. Adjacent cell rows are spaced apart from one another by striplike trench insulator structures. The semiconductor fins are in each case recessed in one or in two inner trench sections by means of gate trenches which extend from a longitudinal side of the respective semiconductor fin to the opposite longitudinal side. By isotropically etching the oxide of the trench insulator structures, pockets (fin trenches) are formed, in a self-aligned manner with respect to the gate trenches in the trench insulator structures and filled with a gate conductor material.

Abstract: A transistor, memory cell array and method of manufacturing a transistor are disclosed.

Abstract: The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which comprises in each case a first gate electrode and also a rear side electrode. The memory cell arrangement contains word lines and also rear side electrode lines which are arranged in each case alternately between adjacent cell columns. The invention provides for in each case the first gate electrodes of adjacent cell columns to be connected to the word line lying between the cell columns and in each case the rear side electrodes of adjacent cell columns to be connected to the rear side line lying between the cell columns. All the rear side lines are held at a constant potential, while for reading from a memory cell that word line is addressed to which the first gate electrode of the memory cell to be read is connected.

Abstract: A DRAM memory cell arrangement having memory cells each having a trench capacitor and a fin field-effect transistor or FinFET for addressing the trench capacitor. The memory cells are arranged in cell rows which are offset with respect to one another and are separated from one another by trench insulator structures. Word lines orthogonal to the cell rows mesh in comblike fashion between the cell rows and alternately traverse trench capacitors and channel regions of fin field-effect transistors. By means of a on-photolithographic mask having mask sections aligned with the trench capacitors, trench-insulator structures are provided in each case between a sidewall gate section of a word line and the adjoining trench capacitor, said trench-insulator structures decoupling the respective trench capacitor from the traversing word line.

Abstract: A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length Leff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends along the x axis and in this case encloses an active zone of the transistor structure from two sides or completely. The effective channel width Weff is dependent on the depth to which the gate electrode is formed. A memory cell having a selection transistor in accordance with the transistor structure has both a low leakage current and a good switching behavior. By a suitable integration concept, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors.