Abstract: An apparatus comprises a branch target buffer (BTB) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the BTB performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. When the BTB is identified in the lookup as storing predicted target addresses for more than one branch instruction in said fetch block, branch target selecting circuitry selects a next fetch block address from among the multiple predicted target addresses returned in the lookup. A shortcut path bypassing the branch target selecting circuitry is provided to forward a predicted target address identified in the lookup as the next fetch block address when a predetermined condition is satisfied.

Abstract: An isolator for suspending a vehicle component from a chassis is provided. The isolator has an elastomeric body defining first and second apertures therethrough. The isolator has a first support bracket extending through a first outer region of the body. A second support bracket extends through a second outer region of the body. The isolator has first and second flexible couplings, with each coupling connecting the first support to the second support. A method of forming the isolator is also provided.

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry is arranged, during each prediction iteration, to make a prediction for a predict block comprising a sequence of M instruction addresses, in order to identify whether that predict block contains the instruction address for an instruction flow changing instruction that is predicted as taken.

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken.

Abstract: A variable noise attenuation element includes at least two tube sections that define an overall tube length that defines a first effective length and associated first peak frequency for noise attenuation, and a valve having a valve member. The valve joins the tube sections together and includes openings that permit communication between the tube sections when the valve is in an open configuration. The valve member operates to close the opening in response to a predetermined vacuum level within the tube sections to define a second tube effective length and associated second peak frequency for attenuation that is less than the overall length. A method of attenuating noise in a vehicle using a passive attenuation arrangement operates a valve disposed between two tube sections to change an effective length of the tube and associated peak frequencies for attenuation in response to an engine operating parameter.

Abstract: Techniques for layout-agnostic complex document processing are described. A document processing service can analyze documents that do not adhere to defined layout rules in an automated manner to determine the content and meaning of a variety of types of segments within the documents. The service may chunk a document into multiple chunks, and operate upon the chunks in parallel by identifying segments within each chunk, classifying the segments into segment types, and processing the segments using special-purpose analysis engines adapted for the analysis of particular segment types to generate results that can be aggregated into an overall output for the entire document that captures the meaning and context of the document text.

Abstract: Apparatus and a method of operating the same is disclosed. Instruction fetch circuitry is provided to fetch a block of instructions from memory and branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions. The branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a subsequent branch status indicator. When there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken the subsequent branch status indicator has a first value, and otherwise the subsequent branch status indicator has a second value. This supports improved handling of a misprediction as taken.

Abstract: A data processing apparatus is provided that includes lookup circuitry to provide first prediction data in respect of a first block of instructions and second prediction data in respect of a second block of instructions. First processing circuitry provides a first control flow prediction in respect of the first block of instructions using the first prediction data and second processing circuitry provides a second control flow prediction in respect of the second block of instructions using the second prediction data. The first block of instructions and the second block of instructions collectively define a prediction block and the lookup circuitry uses a reference to the prediction block as at least part of an index to both the first prediction data and the second prediction data.

Abstract: A data processing apparatus is provided that includes global-history prediction circuitry that provides a prediction of an outcome of a given control flow instruction based on a result of execution of one or more previous control flow instructions. Correction circuitry provides a corrected prediction of the global-history prediction circuitry in respect of the given control flow instruction and cache circuitry, separate from the correction circuitry, stores the corrected prediction in respect of the given control flow instruction.

Abstract: A computer implemented method includes receiving multiple requests to update a data structure stored in non-volatile memory (NVM) and applying an atomic multiword update to the data structure to arbitrate access to the NVM. In a further embodiment, a computer implemented method includes allocating a descriptor for a persistent multi-word compare-and-swap operation (PMwCAS), specifying targeted addresses of words to be modified, returning an error if one of the targeted addresses contains a value not equal to a corresponding compare value, executing the operation atomically if the targeted addresses contain values that match the corresponding compare values, and aborting the operation responsive to the returned error.

Abstract: Systems and methods for token-based cross-currency interoperability are disclosed. In one embodiment, in a first financial institution information processing apparatus comprising at least one computer processor, a method for conducting a token-based cross-currency transaction may include: (1) receiving, from a first party, a transaction initiation request for a transaction amount to a second party; (2) deducting the transaction amount from a fiat currency account for the first party; (3) creating a token amount of tokens for the transaction amount; (4) writing the token amount to a distributed ledger; and (5) transferring the token amount of tokens to a second financial institution for the second party.

Abstract: Branch prediction circuitry processes blocks of instructions and provides instruction fetch circuitry with indications of predicted next blocks of instructions to be retrieved from memory. Main branch target storage stores branch target predictions for branch instructions in the blocks of instructions. Secondary branch target storage caches the branch target predictions from the main branch target storage. Look-ups in the secondary branch target storage and the main branch target storage are performed in parallel. The main branch target storage is set-associative and an entry in the main branch target storage comprises multiple ways, wherein each way of the multiple ways stores a branch target prediction for one branch instruction.

Abstract: An isolator for suspending a vehicle component from a chassis is provided. The isolator has an elastomeric body defining first and second apertures therethrough. The isolator has a first support bracket extending through a first outer region of the body. A second support bracket extends through a second outer region of the body. The isolator has first and second flexible couplings, with each coupling connecting the first support to the second support. A method of forming the isolator is also provided.

Abstract: A method of making a metallic material includes mechanically alloying base metal with corrosion inhibitor to thereby form an alloy having the base metal and the corrosion inhibitor. A method of preventing corrosion includes providing the alloy to a process environment, allowing the process environment to corrode or crack the alloy to thereby expose the corrosion inhibitor of the alloy to the process environment, allowing a first ionic component of the corrosion inhibitor to be transformed to a second ionic component, and allowing the second ionic component to be repassivated with the alloy to thereby prevent further corrosion or cracking of the alloy.

Abstract: A computer implemented method includes receiving multiple requests to update a data structure stored in non-volatile memory (NVM) and applying an atomic multiword update to the data structure to arbitrate access to the NVM. In a further embodiment, a computer implemented method includes allocating a descriptor for a persistent multi-word compare-and-swap operation (PMwCAS), specifying targeted addresses of words to be modified, returning an error if one of the targeted addresses contains a value not equal to a corresponding compare value, executing the operation atomically if the targeted addresses contain values that match the corresponding compare values, and aborting the operation responsive to the returned error.

Abstract: A variable noise attenuation element includes at least two tube sections that define an overall tube length that defines a first effective length and associated first peak frequency for noise attenuation, and a valve having a valve member. The valve joins the tube sections together and includes openings that permit communication between the tube sections when the valve is in an open configuration. The valve member operates to close the opening in response to a predetermined vacuum level within the tube sections to define a second tube effective length and associated second peak frequency for attenuation that is less than the overall length. A method of attenuating noise in a vehicle using a passive attenuation arrangement operates a valve disposed between two tube sections to change an effective length of the tube and associated peak frequencies for attenuation in response to an engine operating parameter.

Abstract: A data processing apparatus contains branch prediction circuitry including a micro branch target buffer, a full branch target buffer and a global history buffer. The branch target buffer entries contain history data which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry is suppressed for these following blocks of program instructions so as to save energy.

Abstract: A variable noise attenuation element includes at least two tube sections that define an overall tube length that defines a first effective length and associated first peak frequency for noise attenuation, and a valve having a valve member. The valve joins the tube sections together and includes openings that permit communication between the tube sections when the valve is in an open configuration. The valve member operates to close the opening in response to a predetermined vacuum level within the tube sections to define a second tube effective length and associated second peak frequency for attenuation that is less than the overall length. A method of attenuating noise in a vehicle using a passive attenuation arrangement operates a valve disposed between two tube sections to change an effective length of the tube and associated peak frequencies for attenuation in response to an engine operating parameter.

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.