Patents by Inventor Umesh Mishra
Umesh Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140231929Abstract: A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.Type: ApplicationFiled: April 24, 2014Publication date: August 21, 2014Applicant: Transphorm Inc.Inventors: Umesh Mishra, Srabanti Chowdhury
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Publication number: 20140231823Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.Type: ApplicationFiled: February 13, 2014Publication date: August 21, 2014Applicant: Transphorm Inc.Inventors: Srabanti Chowdhury, Umesh Mishra, Yuvaraj Dora
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Patent number: 8803313Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.Type: GrantFiled: August 21, 2012Date of Patent: August 12, 2014Assignee: Cree, Inc.Inventors: Umesh Mishra, Primit Parikh, Yifeng Wu
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Patent number: 8803246Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.Type: GrantFiled: July 16, 2012Date of Patent: August 12, 2014Assignee: Transphorm Inc.Inventors: Yifeng Wu, Umesh Mishra, Srabanti Chowdhury
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Patent number: 8742459Abstract: A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.Type: GrantFiled: May 14, 2009Date of Patent: June 3, 2014Assignee: Transphorm Inc.Inventors: Umesh Mishra, Lee McCarthy, Nicholas Fichtenbaum
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Patent number: 8742460Abstract: A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.Type: GrantFiled: December 15, 2010Date of Patent: June 3, 2014Assignee: Transphorm Inc.Inventors: Umesh Mishra, Srabanti Chowdhury
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Publication number: 20140103399Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Publication number: 20140099757Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Transphorm Inc.Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
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Publication number: 20140094010Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: ApplicationFiled: October 31, 2013Publication date: April 3, 2014Applicant: Transphorm Inc.Inventors: Rakesh L. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Patent number: 8664695Abstract: A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor layers, each of which extends from the edge of the gate toward the drain electrode, and each of which is isolated from said semiconductor layers and from the others of the field plates. The topmost of the field plates is electrically connected to the source electrode and the others of the field plates are electrically connected to the gate or the source electrode.Type: GrantFiled: July 2, 2009Date of Patent: March 4, 2014Assignee: Cree, Inc.Inventors: Yifeng Wu, Primit Parikh, Umesh Mishra, Marcia Moore
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Publication number: 20140054603Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.Type: ApplicationFiled: August 22, 2013Publication date: February 27, 2014Applicant: Transphorm Inc.Inventors: Yifeng Wu, Umesh Mishra, Primit Parikh, Rongming Chu, Ilan Ben-Yaacov, Likun Shen
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Publication number: 20140042495Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.Type: ApplicationFiled: October 18, 2013Publication date: February 13, 2014Applicant: Transphorm Inc.Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
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Patent number: 8643062Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.Type: GrantFiled: February 2, 2011Date of Patent: February 4, 2014Assignee: Transphorm Inc.Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
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Patent number: 8633518Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: December 21, 2012Date of Patent: January 21, 2014Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Publication number: 20140015066Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.Type: ApplicationFiled: July 16, 2012Publication date: January 16, 2014Applicant: TRANSPHORM INC.Inventors: Yifeng Wu, Umesh Mishra, Srabanti Chowdhury
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Patent number: 8624662Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.Type: GrantFiled: February 5, 2010Date of Patent: January 7, 2014Assignee: Transphorm Inc.Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
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Publication number: 20140001557Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: TRANSPHORM INC.Inventors: Umesh Mishra, Srabanti Chowdhury, Ilan Ben-Yaacov
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Publication number: 20130344687Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 ?m. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 ?m.Type: ApplicationFiled: August 26, 2013Publication date: December 26, 2013Applicant: Cree, Inc.Inventors: Adam William Saxler, Yifeng Wu, Primit Parikh, Umesh Mishra, Richard Peter Smith, Scott T. Sheppard
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Patent number: 8598937Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: GrantFiled: October 7, 2011Date of Patent: December 3, 2013Assignee: Transphorm Inc.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Publication number: 20130316502Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: July 30, 2013Publication date: November 28, 2013Applicant: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh