Abstract: Apparatus for multiplexing electronic data-words provided by a plurality of input sources operating in accordance with respective input clocks which may be mutually asynchronous. The data-words are multiplexed to a common output operating in accordance with a system clock. The apparatus includes delay circuitry, which generates a plurality of select signals responsive to the system clock, corresponding respectively to the plurality of input sources. The apparatus also includes a plurality of synchronizers respectively associated with the plurality of input sources, each synchronizer including a series of memory buffers through which data-words from the respective input source are transferred. The series of memory buffers includes at least an input buffer, which receives the data-words from the respective input source in accordance with the respective input clock, and an output buffer, which provides the data-words for output in accordance with the corresponding select signal.

Abstract: A PCI system is provided with a shadow register and a shadow timer. When a master device sends an address designating a target device that is connected to another bus, the device's latency value is recorded in the shadow register. While the PCI-PCI bridge arbitrates for the target bus, the master's latency timer increments but the shadow timer will not begin to increment until the PCI-PCI bridge receives a grant# from the target's bus and data transmission begins. Accordingly, the bus arbiter will not de-assert the grant# until the shadow timer has reached the latency value or the master device has released the bus after completing its data transmission. This ensures that the master device will be allocated a time period equal to its latency value to transmit data.