Patents by Inventor Ursula MEYER

Ursula MEYER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip package and a method for manufacturing a chip package
    Patent number: 8841768
    Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: September 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Carsten Von Koblinski, Michael Knabl, Ursula Meyer, Francisco Javier Santos Rodriguez, Alexander Breymesser, Andre Brockmeier
  • CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE
    Publication number: 20140021610
    Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region
    Type: Application
    Filed: July 23, 2012
    Publication date: January 23, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Carsten VON KOBLINSKI, Michael KNABL, Ursula MEYER, Francisco Javier SANTOS RODRIGUEZ, Alexander BREYMESSER, Andre BROCKMEIER