Patents by Inventor Usha Prabhu

Usha Prabhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system to recreate instruction and data traces in an embedded processor
    Patent number: 7490227
    Abstract: A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Goran Bilski, Jorge Ernesto Carrillo, Usha Prabhu, Navaneethan Sundaramoorthy
  • Method and system for fast linked processor in a system on a chip (SoC)
    Patent number: 7340585
    Abstract: A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and 34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 27, 29, 31) coupled among at least two of the plurality processing modules providing a streaming communication channel between at least two of the plurality of processing modules.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: March 4, 2008
    Assignee: Xilinx, Inc.
    Inventors: Satish R. Ganesan, Goran Bilski, Usha Prabhu, Ralph D. Wittig
  • Method and system for designing a multiprocessor
    Patent number: 7310594
    Abstract: A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: December 18, 2007
    Assignee: Xilinx, Inc.
    Inventors: Satish R. Ganesan, Usha Prabhu, Sundararajarao Mohan, Ralph D. Wittig, David W. Bennett
  • Method and apparatus for providing self-implementing hardware-software libraries
    Patent number: 7243330
    Abstract: Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A hardware platform is defined. A software platform is defined having a plurality of software components, including a library. Hardware component dependency data associated with the library is identified. At least one hardware component is added to the hardware platform in response to the hardware component dependency data.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: July 10, 2007
    Assignee: Xilinx, Inc.
    Inventors: Satish R. Ganesan, Amit Kasat, Sathyanarayanan Thammanur, Sundararajarao Mohan, Usha Prabhu, Ralph D. Wittig
  • Generating fast logic simulation models for a PLD design description
    Patent number: 7131091
    Abstract: Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is created. The graph representation includes nodes and edges. From the nodes in the graph representation, a plurality of register nodes are generated to correspond to respective register functions. Logic optimization is performed on nodes that represent combinational logic functions. For each register node and each output node, an evaluation equation is generated after performing logic optimization. For each clock cycle of a logic simulation, each evaluation equation is evaluated and produces an output value for the next clock cycle.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: October 31, 2006
    Assignee: Xilinx, Inc.
    Inventors: Satish R. Ganesan, Goran Bilski, Usha Prabhu, Paulo L. Dutra