Abstract: A fabrication process for a memory structure including three-dimensional arrays of thin-film ferroelectric storage transistors is disclosed. In some embodiments, the ferroelectric storage transistors are organized in three-dimensional arrays of horizontal NOR memory strings. In some embodiments, the fabrication process uses a liner underlayer in the deposition process of the channel layer where the liner underlayer provides a uniform surface for the deposition of the channel layer and also serves as an etch stop layer in the subsequent metal replacement process. In another embodiment, the fabrication process applies a liner layer in vertical shafts during the local word line process to reduce or eliminate irregular features in the local word line structures, thereby enhancing the electrical characteristics and reliability of the memory arrays thus formed.

Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 ?m. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.